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Eles, Petru Ion
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Publications (10 of 245) Show all publications
Zhou, Y., Samii, S., Eles, P. & Peng, Z. (2019). Partitioned and overhead-aware scheduling of mixed-criticality real-time systems. In: 24th Asia and South Pacific Design Automation Conference: . Paper presented at Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 21 - 24, 2019 (pp. 39-44). New York: Association for Computing Machinery (ACM)
Open this publication in new window or tab >>Partitioned and overhead-aware scheduling of mixed-criticality real-time systems
2019 (English)In: 24th Asia and South Pacific Design Automation Conference, New York: Association for Computing Machinery (ACM), 2019, p. 39-44Conference paper, Published paper (Refereed)
Abstract [en]

Modern real-time embedded and cyber-physical systems comprise a large number of applications, often of different criticalities, executing on the same computing platform. Partitioned scheduling is used to provide temporal isolation among tasks with different criticalities. Isolation is often a requirement, for example, in order to avoid the case when a low criticality task overruns or fails in such a way that causes a failure in a high criticality task. When the number of partitions increases in mixed criticality systems, the size of the schedule table can become extremely large, which becomes a critical bottleneck due to design time and memory constraints of embedded systems. In addition, switching between partitions at runtime causes CPU overhead due to preemption. In this paper, we propose a design framework comprising a hyper-period optimization algorithm, which reduces the size of schedule table and preserves schedulability, and a re-scheduling algorithm to reduce the number of preemptions. Extensive experiments demonstrate the effectiveness of proposed algorithms and design framework.

Place, publisher, year, edition, pages
New York: Association for Computing Machinery (ACM), 2019
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-160489 (URN)10.1145/3287624.3287653 (DOI)2-s2.0-85061136107 (Scopus ID)978-1-4503-6007-4 (ISBN)
Conference
Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 21 - 24, 2019
Available from: 2019-09-24 Created: 2019-09-24 Last updated: 2019-10-02Bibliographically approved
Zhou, Y., Samii, S., Eles, P. I. & Peng, Z. (2019). Scheduling optimization with partitioning for mixed-criticality systems. Journal of systems architecture, 98, 191-200
Open this publication in new window or tab >>Scheduling optimization with partitioning for mixed-criticality systems
2019 (English)In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 98, p. 191-200Article in journal (Refereed) Published
Abstract [en]

Modern real-time embedded and cyber-physical systems comprise a large number of applications, often of different criticalities, executing on the same computing platform. Partitioned scheduling is used to provide temporal isolation among tasks with different criticalities. Isolation is often a requirement, for example, in order to avoid the case when a low criticality task overruns or fails in such a way that causes a failure in a high criticality task. When the number of partitions increases in mixed criticality systems, the size of the schedule table can become extremely large, which becomes a critical bottleneck due to design time and memory constraints of embedded systems. In addition, switching between partitions causes CPU overhead due to preemption. In this paper, we propose a design framework comprising the trade-off between schedule table size and system utilization, as well as a re-scheduling algorithm to reduce the effect of preemptions on utilization. Extensive experiments demonstrate the effectiveness of the proposed algorithms and design framework.

Place, publisher, year, edition, pages
Elsevier, 2019
Keywords
Real-time systems, Mixed-criticality systems, Scheduling
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-160490 (URN)10.1016/j.sysarc.2019.07.007 (DOI)2-s2.0-85069685876 (Scopus ID)
Available from: 2019-09-24 Created: 2019-09-24 Last updated: 2019-10-02Bibliographically approved
Horga, A., Chattopadhyay, S., Eles, P. I. & Peng, Z. (2018). Measurement Based Execution Time Analysis of GPGPU Programs via SE+GA. In: : . Paper presented at 2018 21st Euromicro Conference on Digital System Design (DSD). IEEE
Open this publication in new window or tab >>Measurement Based Execution Time Analysis of GPGPU Programs via SE+GA
2018 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Understanding the execution time is critical for embedded, real-time applications. Worst-case execution time (WCET) is an important metric to check the real-time constraints imposed on embedded applications. For complex execution platforms, such as graphics processing units (GPUs), analysis of WCET imposes great challenges due to the complex characteristics of GPU architecture as well as GPU program semantics. In this paper, we propose GDivAn, a measurement-based WCET analysis tool for arbitrary GPU kernels. GDivAn systematically combines the strength of symbolic execution (SE) and genetic algorithm (GA) to maintain both the scalability and the effectiveness of the analysis process. Our evaluation with several open-source GPU kernels reveals the efficiency of GDivAn.

Place, publisher, year, edition, pages
IEEE, 2018
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-152463 (URN)10.1109/DSD.2018.00021 (DOI)978-1-5386-7377-5 (ISBN)978-1-5386-7378-2 (ISBN)
Conference
2018 21st Euromicro Conference on Digital System Design (DSD)
Available from: 2018-11-02 Created: 2018-11-02 Last updated: 2018-11-30
Aminifar, A., Eles, P., Peng, Z., Cervin, A. & Årzén, K.-E. (2017). Control-Quality Driven Design of Embedded Control Systems with Stability Guarantees. IEEE design & test
Open this publication in new window or tab >>Control-Quality Driven Design of Embedded Control Systems with Stability Guarantees
Show others...
2017 (English)In: IEEE design & test, ISSN 2168-2356, E-ISSN 2168-2364Article in journal (Refereed) Published
Abstract [en]

Today, the majority of control applications in embedded systems, e.g., in the automotive domain, are implemented as software tasks on shared platforms. Ignoring implementation impacts during the design of embedded control systems results in complex timing behaviors that may lead to poor performance and, in the worst case, instability of control applications. This article presents a methodology for implementation-aware design of high-quality and stable embedded control systems on shared platforms with complex timing behaviors.

Place, publisher, year, edition, pages
IEEE, 2017
Keywords
Control-Scheduling, Co-Design, Control Performance, Stability, Robustness, Embedded Control Systems, Real-Time Control, Cyber-Physical Systems
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-142784 (URN)10.1109/MDAT.2017.2766564 (DOI)000438755200007 ()2-s2.0-85032440359 (Scopus ID)
Available from: 2017-11-03 Created: 2017-11-03 Last updated: 2018-08-16Bibliographically approved
Ukhov, I., Marculescu, D., Eles, P. I. & Peng, Z. (2017). Fast Synthesis of Power and Temperature Profiles for the Development of Data-Driven Resource Managers. Linköpng: Linköping University Electronic Press
Open this publication in new window or tab >>Fast Synthesis of Power and Temperature Profiles for the Development of Data-Driven Resource Managers
2017 (English)Report (Other academic)
Abstract [en]

The goal of this work is to facilitate the development of proactive power- and temperature-aware resource managers that leverage machine learning in order to attain their objectives. In this context, the availability of sufficiently large amounts of relevant data, which are essential for learning and, therefore, exploration of research ideas, is elusive. In order to fulfill the need, we present a toolchain for fast generation of realistic power and temperature profiles of computer systems. The toolchain provides profuse representative data to learn from during development stages. The overreaching objective is to help research by making it tractable to experiment with the highly promising but data-demanding state-of-the-art techniques for prediction.

Place, publisher, year, edition, pages
Linköpng: Linköping University Electronic Press, 2017. p. 6
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-140757 (URN)
Available from: 2017-09-12 Created: 2017-09-12 Last updated: 2018-01-13Bibliographically approved
Ukhov, I., Marculescu, D., Eles, P. I. & Peng, Z. (2017). Fine-Grained Long-Range Prediction of Resource Usage in Computer Clusters. Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Fine-Grained Long-Range Prediction of Resource Usage in Computer Clusters
2017 (English)Report (Other academic)
Abstract [en]

In order to facilitate the development of intelligent resource managers of computer clusters, we investigate the utility of the state-of-the-art neural networks for the purpose of fine-grained long-range prediction of the resource usage in one such cluster. We consider a large data set of real-life traces and describe in detail our workflow, starting from making the data accessible for learning and finishing by predicting the resource usage of individual tasks multiple steps ahead. The experimental results indicate that such fine-grained traces as the ones considered possess a certain structure, and that this structure can be extracted by advanced machine-learning techniques and subsequently utilized for making informed predictions.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2017. p. 6
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-140756 (URN)
Available from: 2017-09-12 Created: 2017-09-12 Last updated: 2018-01-13Bibliographically approved
Ukhov, I., Eles, P. I. & Peng, Z. (2017). Probabilistic Analysis of Electronic Systems via Adaptive Hierarchical Interpolation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(11), 1883-1896
Open this publication in new window or tab >>Probabilistic Analysis of Electronic Systems via Adaptive Hierarchical Interpolation
2017 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 36, no 11, p. 1883-1896Article in journal (Refereed) Published
Abstract [en]

We present a framework for system-level analysis of electronic systems whose runtime behaviors depend on uncertain parameters. The proposed approach thrives on hierarchical interpolation guided by an advanced adaptation strategy, which makes the framework general and suitable for studying various metrics that are of interest to the designer. Examples of such metrics include the end-to-end delay, total energy consumption, and maximum temperature of the system under consideration. The framework delivers a light generative representation that allows for a straightforward, computationally efficient calculation of the probability distribution and accompanying statistics of the metric at hand. Our technique is illustrated by considering a number of uncertainty-quantification problems and comparing the corresponding results with exhaustive simulations.

Place, publisher, year, edition, pages
IEEE Computer Society, 2017
Keywords
adaptive interpolation, computer simulation, electronic system, probabilistic analysis, sparse grid, statistical dependence, uncertainty quantification
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-140760 (URN)10.1109/TCAD.2017.2705117 (DOI)000413332700010 ()
Available from: 2017-09-12 Created: 2017-09-12 Last updated: 2018-01-13Bibliographically approved
Lifa, A., Eles, P. & Peng, Z. (2016). A Reconfigurable Framework for Performance Enhancement with Dynamic FPGA Configuration Prefetching. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(1), 100-113
Open this publication in new window or tab >>A Reconfigurable Framework for Performance Enhancement with Dynamic FPGA Configuration Prefetching
2016 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 35, no 1, p. 100-113Article in journal (Refereed) Published
Abstract [en]

Many modern applications exhibit a dynamic and nonstationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable field programmable gate array architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx’s commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive application programming interface, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the smallest univalue segment assimilating nucleus image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-the-art prefetching algorithms, with only a minor energy overhead.

Place, publisher, year, edition, pages
IEEE Computer Society, 2016
Keywords
Dynamic configuration prefetching, FPGA, dynamic configuration prefetching, field programmable gate array (FPGA), partial reconfiguration, self-reconfiguring and adaptive platform
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-123741 (URN)10.1109/TCAD.2015.2448694 (DOI)000367338300008 ()
Available from: 2016-01-11 Created: 2016-01-11 Last updated: 2018-01-10Bibliographically approved
Aminifar, A., Bini, E., Eles, P. l. & Peng, Z. (2016). Analysis and Design of Real-Time Servers for Control Applications. I.E.E.E. transactions on computers (Print), 65(3), 834-846
Open this publication in new window or tab >>Analysis and Design of Real-Time Servers for Control Applications
2016 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, no 3, p. 834-846Article in journal (Refereed) Published
Abstract [en]

Today, a considerable portion of embedded systems, e.g., automotive and avionic, comprise several control applications. Guaranteeing the stability of these control applications in embedded systems, or cyber-physical systems, is perhaps the most fundamental requirement while implementing such applications. This is different from the classical hard real-time systems where often the acceptance criterion is meeting the deadline. In other words, in the case of control applications, guaranteeing stability is considered to be a main design goal, which is linked to the amount of delay and jitter a control application can tolerate before instability. This advocates the need for new design and analysis techniques for embedded real-time systems running control applications. In this paper, the analysis and design of such systems considering a server-based resource reservation mechanism are addressed. The benefits of employing servers are manifold: providing a compositional and scalable framework, protection against other tasks misbehaviors, and systematic bandwidth assignment and co-design. We propose a methodology for designing bandwidth-optimal servers to stabilize control tasks. The pessimism involved in the proposed methodology is both discussed theoretically and evaluated experimentally.

Place, publisher, year, edition, pages
IEEE COMPUTER SOC, 2016
Keywords
Embedded systems; real-time systems; real-time control co-design; control server; stability; bandwidth minimization
National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-126249 (URN)10.1109/TC.2015.2435789 (DOI)000370729600014 ()
Note

Funding Agencies|ELLIIT Excellence Center; Linneaus Center LCCC; Marie Curie Intra European Fellowship within Seventh European Community Framework Programme; Swedish Research Council

Available from: 2016-03-21 Created: 2016-03-21 Last updated: 2018-01-10
Tanasa, B., Bordoloi, U. D., Eles, P. & Peng, Z. (2016). Correlation-Aware Probabilistic Timing Analysis for the Dynamic Segment of FlexRay. ACM Transactions on Embedded Computing Systems, 15(3), 54:1-54:31
Open this publication in new window or tab >>Correlation-Aware Probabilistic Timing Analysis for the Dynamic Segment of FlexRay
2016 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 15, no 3, p. 54:1-54:31Article in journal (Refereed) Published
Abstract [en]

We propose an analytical framework for probabilistic timing analysis of the event-triggered Dynamic segment of the FlexRay communication protocol. Specifically, our framework computes the Deadline Miss Ratio of each message. The core problem is formulated as a Mixed Integer Linear Program (MILP). Given the intractability of the problem, we also propose several techniques that help to mitigate the running times of our tool. This includes the re-engineering of the problem to run it on GPUs as well as reformulating the MILP itself.

Most importantly, we also show how our framework can handle correlations between the queuing events of messages. This is challenging because one cannot apply the convolution operator in the same way as in the case of independent queuing events.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2016
Keywords
Automotive networks, correlations, deadline miss ratio, dynamic seg- ment, flexray, probabilistic analysis, timing analysis
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-128836 (URN)10.1145/2870635 (DOI)000381422700015 ()
Available from: 2016-06-01 Created: 2016-06-01 Last updated: 2018-01-10
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