Time-sensitive networking (TSN) is an emerging technology widely used in real-time systems for its high bandwidth and deterministic timing properties. To ensure the deterministic transmission of Time-triggered (TT) messages, a guard band mechanism is employed to prevent interference from other messages, such as Audio-Video Bridging (AVB) and Best-effort (BE) messages, before transmitting the TT messages in TSN. However, this mechanism introduces transmission delays for non-TT messages and bandwidth wastes for the physical links. Another challenge arises from the default First-in-first-out (FIFO) order of incoming messages, resulting in a relatively low acceptance rate for non-TT messages. To address these issues, a hybrid scheduling algorithm based on the min-heap structure (HSMH) is proposed. For AVB messages, HSMH sorts them in ascending style on the basis of deadlines, guaranteeing the earliest deadline message to be sent first. For BE messages, a threshold is designed to diverge them into two queues: a FIFO queue and a STF (shortest-time-first) queue. The former outputs the messages in a FIFO style, while the latter outputs messages in a STF style. All the output order of AVB messages and STF-queue messages are arranged in a min-heap structure. The algorithm can efficiently improve the transmission rate of AVB messages, the sending rate of BE messages, and the overall link utilization. Experimental results demonstrate that the proposed algorithm outperforms existing approaches in all these three aspects.

This paper presents a Relative-Priority Genetic Algorithm (RPGA) designed for tackling Integrated Mapping and Scheduling (IMS) problems, frequently encountered in High-Level Synthesis. RPGA features a unique encoding and decoding mechanism specifically crafted for IMS problems, notably those involving OR nodes that denote alternative operation paths. Through comprehensive benchmarking experiments, RPGA demonstrates remarkable superiority in solution quality and convergence speed when compared to established meta-heuristics.

The fifth-generation (5G) technology standard in telecommunications is expected to support ultra-reliable low latency communication to enable real-time applications such as industrial automation and control. 5G configured grant (CG) scheduling features a pre-allocated periodicity-based scheduling approach, which reduces control signaling time and guarantees service quality. Although this enables 5G to support hard real-time periodic traffics, synthesizing the schedule efficiently and achieving high resource efficiency, while serving multiple communications, are still an open problem. In this work, we study the trade-off between scheduling flexibility and control overhead when performing CG scheduling. To address the CG scheduling problem, we first formulate it using satisfiability modulo theories (SMT) so that an SMT solver can be used to generate optimal solutions. To enhance scalability, we propose two heuristic approaches. The first one as the baseline, Co1, follows the basic idea of the 5G CG scheduling scheme that minimizes the control overhead. The second one, CoU, enables increased scheduling flexibility while considering the involved control overhead. The effectiveness and scalability of the proposed techniques and the superiority of CoU compared to Co1 have been evaluated using a large number of generated benchmarks as well as a realistic case study for industrial automation.

Amid growing concerns about hardware security, comprehensive security testing has become essential for chip certification. This article proposes a deep-testing method for identifying Trojans of particular concern to middle-to-high-end users, with a focus on illegal instructions. A hidden instruction Trojan can employ a low-probability sequence of normal instructions as a boot sequence, which is followed by an illegal instruction that triggers the Trojan. This enables the Trojan to remain deeply hidden within the processor. It then exploits an intrusion mechanism to acquire Linux control authority by setting a hidden interrupt as its payload. We have developed an unbounded model checking (UMC) technique to uncover such Trojans. The proposed UMC technique has been optimized with slicing based on the input cone, head-point replacement, and backward implication. Our experimental results demonstrate that the presented instruction Trojans can survive detection by existing methods, thus allowing normal users to steal root user privileges and compromising the security of processors. Moreover, our proposed deep-testing method is empirically shown to be a powerful and effective approach for detecting these instruction Trojans.

Modern-day control applications increasingly rely on cyber-physical systems (CPS) to implement advanced functionalities. Notable examples within automotive domains include adaptive cruise control, intelligent navigation, and autonomous driving. Leveraging the cloud's virtually infinite storage and computational power proves to be an efficient strategy for executing these sophisticated control algorithms. However, migrating control computations to the cloud introduces new challenges, notably on security and real-time constraints. We will present an integrated design and optimization methodology tailored for cloud-based control systems. This approach addresses security concerns and other crucial CPS design prerequisites, particularly focusing on ensuring the security and stability mandates of control loops closed over the cloud.

Modern embedded platforms need sophisticated resource managers to utilize their heterogeneous computational resources efficiently. Furthermore, such platforms are subject to fluctuating workloads that are unforeseeable at design time. Predicting the incoming workload could enhance the efficiency of resource management in this situation. But is that the case? And, if so, how substantial is this improvement? Does multiple-step-ahead prediction of the workload contribute to this improvement? How precise must the prediction be to improve decisions rather than cause harm? By proposing a prediction-based resource manager that aims at meeting task deadlines while minimizing energy usage, and by conducting extensive tests, we attempt to provide answers to the aforementioned questions.

Cyber-physical systems (CPS) are widely used for safety-critical applications, including automotive electronics and medical equipment, where reliability and performance are important issues to consider. In the meantime, as the feature sizes of VLSI circuits used in CPS continue to shrink, the power density has increased rapidly, causing a significant rise in chip temperatures. These elevated temperatures have an adverse impact on the system's reliability, performance, and power efficiency. Therefore, it is essential to consider thermal effects during the CPS design process, in particular at the system design level. This paper discusses the challenges of designing and optimizing a CPS, with a focus on the interplay between thermal issues and the stringent reliability and real-time requirements demanded by safety-critical CPS applications. Through this discussion, we will explore the various issues related to CPS design and optimization in the context of different thermal problems. We will also present a temperature-aware task scheduling and mapping technique for heterogeneous CPS platforms consisting of microprocessor cores, GPU processors, and FPGA units. By carefully analyzing and considering thermal impacts during the design process, we can ensure that the CPS to be designed meets the high standards required for safety-critical applications.

This article presents a bounded model checking (BMC)-based temperature-aware software-based self-testing (SBST) technique to test worst case delay faults within the highest temperature range. The BMC-based SBST method first defines the sequential constraint. It develops a sequentially constrained automatic test pattern generation (ATPG) to ensure that the generated delay test patterns can emerge in functional mode. It then uses the processors multiple-level information to reduce the model complexity, avoid aborts due to time-outs during the BMC process, and generate test programs automatically. A temperature-aware SBST method has then been developed to ensure that the test temperature is within the specified range and test the worst case delays under high temperature. Experimental results demonstrate that the proposed technique achieves an extremely high coverage for delay faults and effectively avoids yield loss caused by the overtesting problem. Its test quality also outperforms that of the existing methods. The generated SBST programs are successful and efficient in testing worst case delay faults under high temperature.

Graphic processing units (GPUs) are routinely used for general purpose computations to improve performance. To achieve the sought performance gains, care must be invested in fine tuning the way GPU programs interact with the underlying architecture, accounting for the shared memory bank conflicts and the entailed shared memory transactions. Uncovering inputs leading to particular bank conflicts can turn out to be quite hard given the intricacy of the access patterns and their dependence on the inputs. We propose a symbolic execution based framework to systematically uncover shared memory bank conflicts, to propose inputs to realize a given number of shared memory transactions, and to refute the existence of such inputs if the number of shared memory transactions is impossible to achieve during the execution. This allows programmers to more formally reason about the shared memory conflicts and to validate their impact on performance and security. We have implemented our approach and report on our experiments to explore its usefulness towards performance enhancement and quantifying shared memory side-channel leakage in security applications.