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Peng , Zebo
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Aminifar, A., Eles, P., Peng, Z., Cervin, A. & Årzén, K.-E. (2017). Control-Quality Driven Design of Embedded Control Systems with Stability Guarantees. IEEE design & test.
Open this publication in new window or tab >>Control-Quality Driven Design of Embedded Control Systems with Stability Guarantees
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2017 (English)In: IEEE design & test, ISSN 2168-2356, E-ISSN 2168-2364Article in journal (Refereed) Published
Abstract [en]

Today, the majority of control applications in embedded systems, e.g., in the automotive domain, are implemented as software tasks on shared platforms. Ignoring implementation impacts during the design of embedded control systems results in complex timing behaviors that may lead to poor performance and, in the worst case, instability of control applications. This article presents a methodology for implementation-aware design of high-quality and stable embedded control systems on shared platforms with complex timing behaviors.

Place, publisher, year, edition, pages
IEEE, 2017
Keyword
Control-Scheduling, Co-Design, Control Performance, Stability, Robustness, Embedded Control Systems, Real-Time Control, Cyber-Physical Systems
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-142784 (URN)10.1109/MDAT.2017.2766564 (DOI)2-s2.0-85032440359 (Scopus ID)
Available from: 2017-11-03 Created: 2017-11-03 Last updated: 2018-01-13Bibliographically approved
Ukhov, I., Marculescu, D., Eles, P. I. & Peng, Z. (2017). Fast Synthesis of Power and Temperature Profiles for the Development of Data-Driven Resource Managers. Linköpng: Linköping University Electronic Press.
Open this publication in new window or tab >>Fast Synthesis of Power and Temperature Profiles for the Development of Data-Driven Resource Managers
2017 (English)Report (Other academic)
Abstract [en]

The goal of this work is to facilitate the development of proactive power- and temperature-aware resource managers that leverage machine learning in order to attain their objectives. In this context, the availability of sufficiently large amounts of relevant data, which are essential for learning and, therefore, exploration of research ideas, is elusive. In order to fulfill the need, we present a toolchain for fast generation of realistic power and temperature profiles of computer systems. The toolchain provides profuse representative data to learn from during development stages. The overreaching objective is to help research by making it tractable to experiment with the highly promising but data-demanding state-of-the-art techniques for prediction.

Place, publisher, year, edition, pages
Linköpng: Linköping University Electronic Press, 2017. 6 p.
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-140757 (URN)
Available from: 2017-09-12 Created: 2017-09-12 Last updated: 2018-01-13Bibliographically approved
Ukhov, I., Marculescu, D., Eles, P. I. & Peng, Z. (2017). Fine-Grained Long-Range Prediction of Resource Usage in Computer Clusters. Linköping: Linköping University Electronic Press.
Open this publication in new window or tab >>Fine-Grained Long-Range Prediction of Resource Usage in Computer Clusters
2017 (English)Report (Other academic)
Abstract [en]

In order to facilitate the development of intelligent resource managers of computer clusters, we investigate the utility of the state-of-the-art neural networks for the purpose of fine-grained long-range prediction of the resource usage in one such cluster. We consider a large data set of real-life traces and describe in detail our workflow, starting from making the data accessible for learning and finishing by predicting the resource usage of individual tasks multiple steps ahead. The experimental results indicate that such fine-grained traces as the ones considered possess a certain structure, and that this structure can be extracted by advanced machine-learning techniques and subsequently utilized for making informed predictions.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2017. 6 p.
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-140756 (URN)
Available from: 2017-09-12 Created: 2017-09-12 Last updated: 2018-01-13Bibliographically approved
Ukhov, I., Eles, P. I. & Peng, Z. (2017). Probabilistic Analysis of Electronic Systems via Adaptive Hierarchical Interpolation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(11), 1883-1896.
Open this publication in new window or tab >>Probabilistic Analysis of Electronic Systems via Adaptive Hierarchical Interpolation
2017 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 36, no 11, 1883-1896 p.Article in journal (Refereed) Published
Abstract [en]

We present a framework for system-level analysis of electronic systems whose runtime behaviors depend on uncertain parameters. The proposed approach thrives on hierarchical interpolation guided by an advanced adaptation strategy, which makes the framework general and suitable for studying various metrics that are of interest to the designer. Examples of such metrics include the end-to-end delay, total energy consumption, and maximum temperature of the system under consideration. The framework delivers a light generative representation that allows for a straightforward, computationally efficient calculation of the probability distribution and accompanying statistics of the metric at hand. Our technique is illustrated by considering a number of uncertainty-quantification problems and comparing the corresponding results with exhaustive simulations.

Place, publisher, year, edition, pages
IEEE Computer Society, 2017
Keyword
adaptive interpolation, computer simulation, electronic system, probabilistic analysis, sparse grid, statistical dependence, uncertainty quantification
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-140760 (URN)10.1109/TCAD.2017.2705117 (DOI)000413332700010 ()
Available from: 2017-09-12 Created: 2017-09-12 Last updated: 2018-01-13Bibliographically approved
Lifa, A., Eles, P. & Peng, Z. (2016). A Reconfigurable Framework for Performance Enhancement with Dynamic FPGA Configuration Prefetching. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(1), 100-113.
Open this publication in new window or tab >>A Reconfigurable Framework for Performance Enhancement with Dynamic FPGA Configuration Prefetching
2016 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 35, no 1, 100-113 p.Article in journal (Refereed) Published
Abstract [en]

Many modern applications exhibit a dynamic and nonstationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable field programmable gate array architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx’s commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive application programming interface, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the smallest univalue segment assimilating nucleus image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-the-art prefetching algorithms, with only a minor energy overhead.

Place, publisher, year, edition, pages
IEEE Computer Society, 2016
Keyword
Dynamic configuration prefetching, FPGA, dynamic configuration prefetching, field programmable gate array (FPGA), partial reconfiguration, self-reconfiguring and adaptive platform
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-123741 (URN)10.1109/TCAD.2015.2448694 (DOI)000367338300008 ()
Available from: 2016-01-11 Created: 2016-01-11 Last updated: 2018-01-10Bibliographically approved
Aminifar, A., Bini, E., Eles, P. l. & Peng, Z. (2016). Analysis and Design of Real-Time Servers for Control Applications. I.E.E.E. transactions on computers (Print), 65(3), 834-846.
Open this publication in new window or tab >>Analysis and Design of Real-Time Servers for Control Applications
2016 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, no 3, 834-846 p.Article in journal (Refereed) Published
Abstract [en]

Today, a considerable portion of embedded systems, e.g., automotive and avionic, comprise several control applications. Guaranteeing the stability of these control applications in embedded systems, or cyber-physical systems, is perhaps the most fundamental requirement while implementing such applications. This is different from the classical hard real-time systems where often the acceptance criterion is meeting the deadline. In other words, in the case of control applications, guaranteeing stability is considered to be a main design goal, which is linked to the amount of delay and jitter a control application can tolerate before instability. This advocates the need for new design and analysis techniques for embedded real-time systems running control applications. In this paper, the analysis and design of such systems considering a server-based resource reservation mechanism are addressed. The benefits of employing servers are manifold: providing a compositional and scalable framework, protection against other tasks misbehaviors, and systematic bandwidth assignment and co-design. We propose a methodology for designing bandwidth-optimal servers to stabilize control tasks. The pessimism involved in the proposed methodology is both discussed theoretically and evaluated experimentally.

Place, publisher, year, edition, pages
IEEE COMPUTER SOC, 2016
Keyword
Embedded systems; real-time systems; real-time control co-design; control server; stability; bandwidth minimization
National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-126249 (URN)10.1109/TC.2015.2435789 (DOI)000370729600014 ()
Note

Funding Agencies|ELLIIT Excellence Center; Linneaus Center LCCC; Marie Curie Intra European Fellowship within Seventh European Community Framework Programme; Swedish Research Council

Available from: 2016-03-21 Created: 2016-03-21 Last updated: 2018-01-10
Tanasa, B., Bordoloi, U. D., Eles, P. & Peng, Z. (2016). Correlation-Aware Probabilistic Timing Analysis for the Dynamic Segment of FlexRay. ACM Transactions on Embedded Computing Systems, 15(3), 54:1-54:31.
Open this publication in new window or tab >>Correlation-Aware Probabilistic Timing Analysis for the Dynamic Segment of FlexRay
2016 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 15, no 3, 54:1-54:31 p.Article in journal (Refereed) Published
Abstract [en]

We propose an analytical framework for probabilistic timing analysis of the event-triggered Dynamic segment of the FlexRay communication protocol. Specifically, our framework computes the Deadline Miss Ratio of each message. The core problem is formulated as a Mixed Integer Linear Program (MILP). Given the intractability of the problem, we also propose several techniques that help to mitigate the running times of our tool. This includes the re-engineering of the problem to run it on GPUs as well as reformulating the MILP itself.

Most importantly, we also show how our framework can handle correlations between the queuing events of messages. This is challenging because one cannot apply the convolution operator in the same way as in the case of independent queuing events.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2016
Keyword
Automotive networks, correlations, deadline miss ratio, dynamic seg- ment, flexray, probabilistic analysis, timing analysis
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-128836 (URN)10.1145/2870635 (DOI)000381422700015 ()
Available from: 2016-06-01 Created: 2016-06-01 Last updated: 2018-01-10
Ganjei, Z., Rezine, A., Eles, P. & Peng, Z. (2016). Counting dynamically synchronizing processes. International Journal on Software Tools for Technology Transfer (STTT), 18(5), 517-534.
Open this publication in new window or tab >>Counting dynamically synchronizing processes
2016 (English)In: International Journal on Software Tools for Technology Transfer (STTT), ISSN 1433-2779, E-ISSN 1433-2787, Vol. 18, no 5, 517-534 p.Article in journal (Refereed) Published
Abstract [en]

We address the problem of automatically establishing correctness for programs generating an arbitrary number of concurrent processes and manipulating variables ranging over an infinite domain. The programs we consider can make use of the shared variables to count and synchronize the spawned processes. This allows them to implement intricate synchronization mechanisms, such as barriers. Automatically verifying correctness, and deadlock freedom, of such programs is beyond the capabilities of current techniques. For this purpose, we make use of counting predicates that mix counters referring to the number of processes satisfying certain properties and variables directly manipulated by the concurrent processes. We then combine existing works on counter, predicate, and constrained monotonic abstraction and build a nested counter example based refinement scheme for establishing correctness (expressed as non-reachability of configurations satisfying counting predicates formulas). We have implemented a tool (Pacman, for predicated constrained monotonic abstraction) and used it to perform parameterized verification on several programs whose correctness crucially depends on precisely capturing the number of processes synchronizing using shared variables.

Place, publisher, year, edition, pages
Springer Berlin/Heidelberg, 2016
Keyword
Parameterized verification, Counting predicate, Barrier synchronization, Deadlock freedom, Multithreaded programs, Counter abstraction, Predicate abstraction, Constrained monotonic abstraction
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-124406 (URN)10.1007/s10009-015-0411-0 (DOI)000382011100004 ()
Note

Funding agencies: 12.04 CENIIT project

Available from: 2016-01-28 Created: 2016-01-28 Last updated: 2018-01-10
Ganjei, Z., Rezine, A., Eles, P. & Peng, Z. (2016). Lazy Constrained Monotonic Abstraction. In: Barbara Jobstmann; K. Rustan M. Leino (Ed.), Verification, Model Checking, and Abstract Interpretation: 17th International Conference, VMCAI 2016, St. Petersburg, FL, USA, January 17-19, 2016. Proceedings. Paper presented at 17th International Conference, VMCAI 2016, St. Petersburg, FL, USA, January 17-19, 2016 (pp. 147-165). Springer Berlin/Heidelberg, 9583.
Open this publication in new window or tab >>Lazy Constrained Monotonic Abstraction
2016 (English)In: Verification, Model Checking, and Abstract Interpretation: 17th International Conference, VMCAI 2016, St. Petersburg, FL, USA, January 17-19, 2016. Proceedings / [ed] Barbara Jobstmann; K. Rustan M. Leino, Springer Berlin/Heidelberg, 2016, Vol. 9583, 147-165 p.Conference paper, Published paper (Refereed)
Abstract [en]

We introduce Lazy Constrained Monotonic Abstraction (lazy CMA for short) for lazily and soundly exploring well structured abstractions of infinite state non-monotonic systems. CMA makes use of infinite state and well structured abstractions by forcing monotonicity wrt. refinable orderings. The new orderings can be refined based on obtained false positives in a CEGAR like fashion. This allows for the verification of systems that are not monotonic and are hence inherently beyond the reach of classical analysis based on the theory of well structured systems. In this paper, we consistently improve on the existing approach by localizing refinements and by avoiding to trash the explored state space each time a refinement step is required for the ordering. To this end, we adapt ideas from classical lazy predicate abstraction and explain how we address the fact that the number of control points (i.e., minimal elements to be visited) is a priori unbounded. This is unlike the case of plain lazy abstraction which relies on the fact that the number of control locations is finite. We propose several heuristics and report on our experiments using our open source prototype. We consider both backward and forward explorations on non-monotonic systems automatically derived from concurrent programs. Intuitively, the approach could be regarded as using refinable upward closure operators as localized widening operators for an a priori arbitrary number of control points.

Place, publisher, year, edition, pages
Springer Berlin/Heidelberg, 2016
Series
Lecture Notes in Computer Science, ISSN 0302-9743 (print), 1611-3349 (online)
Keyword
Constrained monotonic abstraction, Lazy exploration, Well structured systems, Safety properties, Counter machines reachability
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-123739 (URN)10.1007/978-3-662-49122-5_7 (DOI)000375148800007 ()9783662491218 (ISBN)9783662491225 (ISBN)
Conference
17th International Conference, VMCAI 2016, St. Petersburg, FL, USA, January 17-19, 2016
Available from: 2016-01-11 Created: 2016-01-11 Last updated: 2018-01-10Bibliographically approved
Jiang, K., Eles, P. & Peng, Z. (2016). Power-Aware Design Techniques of Secure Multimode Embedded Systems. ACM Transactions on Embedded Computing Systems, 15, 6:1-6:29.
Open this publication in new window or tab >>Power-Aware Design Techniques of Secure Multimode Embedded Systems
2016 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 15, 6:1-6:29 p.Article in journal (Refereed) Published
Abstract [en]

Nowadays, embedded systems have been widely used in all types of application areas, some of which belong to the safety and reliability critical domains. The functional correctness and design robustness of the embedded systems involved in such domains are crucial for the safety of personal/enterprise property or even human lives. Thereby, a holistic design procedure that considers all the important design concerns is essential.

In this article, we approach embedded systems design from an integral perspective. We consider not only the classic real-time and quality of service requirements, but also the emerging security and power efficiency demands. Modern embedded systems are not any more developed for a fixed purpose, but instead designed for undertaking various processing requests. This leads to the concept of multimode embedded systems, in which the number and nature of active tasks change during runtime. Under dynamic situations, providing high performance along with various design concerns becomes a really difficult problem. Therefore, we propose a novel power-aware secure embedded systems design framework that efficiently solves the problem of runtime quality optimization with security and power constraints. The efficiency of our proposed techniques are evaluated in extensive experiments.

National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-128182 (URN)10.1145/2801152 (DOI)
Available from: 2016-05-20 Created: 2016-05-20 Last updated: 2018-01-10
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