liu.seSearch for publications in DiVA
Change search
Link to record
Permanent link

Direct link
Johansson, Håkan
Publications (10 of 177) Show all publications
Moryakova, O. & Johansson, H. (2023). Frequency-Domain Implementations of Variable Digital FIR Filters Using the Overlap-Save Technique. In: 2023 24th International Conference on Digital Signal Processing (DSP): . Paper presented at 24th International Conference on Digital Signal Processing (DSP), Rhodes, Greece, June 11-13, 2023. Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Frequency-Domain Implementations of Variable Digital FIR Filters Using the Overlap-Save Technique
2023 (English)In: 2023 24th International Conference on Digital Signal Processing (DSP), Institute of Electrical and Electronics Engineers (IEEE), 2023Conference paper, Published paper (Refereed)
Abstract [en]

The paper introduces frequency-domain implementations of variable digital filters using the overlap-save method. Expressions for implementation and design complexities are derived for real-valued impulse responses. Design examples include implementations of a variable bandwidth (VBW) filter alone as well as a cascade of a VBW filter and a variable fractional delay(VFD) filter. Compared to a time-domain implementation and a filter bank approach, the proposed structures can reduce the implementation complexity significantly and achieve savings up to 95% in the multiplication rate and up to 89% in the addition rate.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Series
International Conference on Digital Signal Processing (DSP), ISSN 1546-1874, E-ISSN 2165-3577
Keywords
Variable digital filter, frequency-domain implementations, implementation complexity, overlap-save
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-201232 (URN)10.1109/DSP58604.2023.10167923 (DOI)2-s2.0-85165482542 (Scopus ID)9798350339598 (ISBN)9798350339604 (ISBN)
Conference
24th International Conference on Digital Signal Processing (DSP), Rhodes, Greece, June 11-13, 2023
Available from: 2024-02-28 Created: 2024-02-28 Last updated: 2024-03-04Bibliographically approved
Rodríguez Linares, D. & Johansson, H. (2023). Low-Complexity Memoryless Linearizer for Analog-to-Digital Interfaces. In: 2023 24th International Conference on Digital Signal Processing (DSP): . Paper presented at 2023 24th International Conference on Digital Signal Processing (DSP), Rhodes (Rodos), Greece, 11-13 June, 2023.. Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Low-Complexity Memoryless Linearizer for Analog-to-Digital Interfaces
2023 (English)In: 2023 24th International Conference on Digital Signal Processing (DSP), Institute of Electrical and Electronics Engineers (IEEE), 2023Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a low-complexity memoryless linearizer for suppression of distortion in analog-to-digital interfaces. It is inspired by neural networks, but has a substantially lower complexity than the neural network schemes that have appeared earlier in the literature in this context. The paper demonstrates that the proposed linearizer can outperform the conventional parallel memoryless Hammerstein linearizer even when the nonlinearities have been generated through a memoryless polynomial model. Further, a design procedure is proposed in which the linearizer parameters are obtained through matrix inversion. Thereby, the costly and time consuming it- erative nonconvex optimization that is traditionally used when training neural networks is eliminated. Moreover, the design and evaluation incorporate a large set of multi-tone signals covering the first Nyquist band. Simulations show signal-to-noise-and-distortion ratio (SNDR) improvements of some 25 dB for multi-tone signals that correspond to the quadrature parts of OFDM signals with QPSK modulation.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Series
International Conference on Digital Signal Processing (DSP), ISSN 1546-1874, E-ISSN 2165-3577
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-201140 (URN)10.1109/DSP58604.2023.10167765 (DOI)2-s2.0-85165488092 (Scopus ID)9798350339598 (ISBN)9798350339604 (ISBN)
Conference
2023 24th International Conference on Digital Signal Processing (DSP), Rhodes (Rodos), Greece, 11-13 June, 2023.
Funder
ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications, B02
Available from: 2024-02-23 Created: 2024-02-23 Last updated: 2024-02-28Bibliographically approved
Wang, Y., Liu, X., Johansson, H., Zhao, C., Chen, K. & Zhu, X. (2020). On first-order compensation of timing mismatch in two-channel TIADCs. In: 2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS): . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS), ELECTR NETWORK, oct 10-21, 2020. IEEE
Open this publication in new window or tab >>On first-order compensation of timing mismatch in two-channel TIADCs
Show others...
2020 (English)In: 2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2020Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, two first-order compensation strategies for timing mismatch in two-channel time-interleaved analog-to-digital converters (TIADCs) are analyzed, and expressions for the spurious-free dynamic range (SFDR) after compensation are derived. The derived expressions reveal that the strategy where both channels are compensated to match each other, using half the value of the mismatch with different signs, achieves a substantially greater SFDR than the strategy where only one channel is compensated to match the other (reference) channel. This is because, after compensation, the remaining aliasing distortion is shown to be of third order in the former strategy whereas it is of second order in the latter. Simulations included demonstrate the validity of the derived expressions.

Place, publisher, year, edition, pages
IEEE, 2020
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Keywords
TIADCs; timing mismatch; compensation; undersampling
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-179878 (URN)10.1109/ISCAS45731.2020.9181227 (DOI)000706854700409 ()9781728133201 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), ELECTR NETWORK, oct 10-21, 2020
Note

Funding: National Natural Science Foundation of ChinaNational Natural Science Foundation of China (NSFC) [61701509]; Science and Technology on Analog Integrated Circuit Laboratory [JCKY2019210C027]

Available from: 2021-10-04 Created: 2021-10-04 Last updated: 2021-11-17
Wang, Y., Johansson, H., Xu, H. & Diao, J. (2016). Bandwidth-efficient calibration method for nonlinear errors in M-channel time-interleaved ADCs. Analog Integrated Circuits and Signal Processing, 86(2), 275-288
Open this publication in new window or tab >>Bandwidth-efficient calibration method for nonlinear errors in M-channel time-interleaved ADCs
2016 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 2, p. 275-288Article in journal (Refereed) Published
Abstract [en]

In order to enhance the effective resolution of time-interleaved analog-to-digital converters (TI-ADCs), both linear and nonlinear channel mismatches should be carefully calibrated. This paper concentrates on a bandwidth-efficient background calibration method for nonlinear errors in M-channel TI-ADCs. It utilizes the least-mean square algorithm as well as a certain degree of oversampling to achieve adaptive mismatch tracking. The calibration performance and computational complexity are investigated and evaluated through behavioral-level simulations. Furthermore, a calibration strategy for narrow-band input signals is proposed and verified as an improvement of the basic calibration structure for such signals.

Place, publisher, year, edition, pages
SPRINGER, 2016
Keywords
Background Calibration; Bandwidth efficient; Nonlinear errors; M-channel; Time-interleaved ADCs
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-124626 (URN)10.1007/s10470-015-0677-x (DOI)000368182800012 ()
Available from: 2016-02-09 Created: 2016-02-08 Last updated: 2017-11-30
Wang, Y., Johansson, H. & Xu, H. (2015). Adaptive Background Estimation for Static Nonlinearity Mismatches in Two-Channel TIADCs. IEEE Transactions on Circuits and Systems - II - Express Briefs, 62(3), 226-230
Open this publication in new window or tab >>Adaptive Background Estimation for Static Nonlinearity Mismatches in Two-Channel TIADCs
2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 3, p. 226-230Article in journal (Refereed) Published
Abstract [en]

Due to channel mismatches in time-interleaved analog-to-digital converters (TIADCs), estimation and compensation methods are required to restore the resolution of the individual converters. Whereas several methods exist for linear mismatches, nonlinearity mismatches have not been widely investigated. This brief presents an adaptive background estimation method for nonlinearity mismatches in two-channel TIADCs. It utilizes a normalized least-mean-square algorithm and assumes slight oversampling as well as a polynomial nonlinearity model that is appropriate when smooth errors dominate. Furthermore, two implementation strategies are proposed to enhance its ability for different applications. The estimation performance of the proposed method is evaluated through behavioral-level simulations.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
Keywords
Adaptive; analog-to-digital converter (ADC); background estimation; nonlinearity mismatches; polynomial models; time interleaving
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-116960 (URN)10.1109/TCSII.2014.2368976 (DOI)000350884900003 ()
Available from: 2015-04-10 Created: 2015-04-10 Last updated: 2017-12-04
Gustafsson, O. & Johansson, H. (2015). Decimation Filters for High-Speed Delta-Sigma Modulators With Passband Constraints: General Versus CIC-Based FIR Filters. In: 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS): . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 2205-2208). IEEE conference proceedings
Open this publication in new window or tab >>Decimation Filters for High-Speed Delta-Sigma Modulators With Passband Constraints: General Versus CIC-Based FIR Filters
2015 (English)In: 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE conference proceedings, 2015, p. 2205-2208Conference paper, Published paper (Refereed)
Abstract [en]

For high-speed delta-sigma modulators the decimation filters are typically polyphase FIR filters as the recursive CIC filters can not be implemented because of the iteration period bound. In addition, the high clock frequency and short input word length make multiple constant multiplication techniques less beneficial. Instead a realistic complexity measure in this setting is the number of non-zero digits of the FIR filter tap coefficients. As there is limited control of the passband approximation error for CIC-based filters these must in most cases be compensated to meet a passband specification. In this work we investigate the complexity of decimation filters meeting CIC-like stopband behavior, but with a well defined passband approximation error. It is found that the general approach can in many cases produce filters with much smaller passband approximation error at a similar complexity.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2015
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-114500 (URN)10.1109/ISCAS.2015.7169119 (DOI)000371471002135 ()978-1-4799-8391-9 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS)
Funder
eLLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications
Available from: 2015-02-24 Created: 2015-02-24 Last updated: 2016-04-07
Eghbali, A. & Johansson, H. (2015). Design of Modulated Filter Banks and Transmultiplexers With Unified Initial Solutions and Very Few Unknown Parameters. IEEE Transactions on Circuits and Systems - II - Express Briefs, 62(4), 397-401
Open this publication in new window or tab >>Design of Modulated Filter Banks and Transmultiplexers With Unified Initial Solutions and Very Few Unknown Parameters
2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 4, p. 397-401Article in journal (Refereed) Published
Abstract [en]

This brief proposes a method for designing modulated filter banks (FBs) with a large number of channels. The impulse response of the long prototype filter is parameterized in terms of a few short impulse responses, thus significantly reducing the number of unknown parameters. The proposed method starts by first obtaining an FB with a few channels. The solution of this FB is then partly reused as an initial (very close to final) solution in the design of FBs with a large number of channels. The number of unknown parameters hence drastically reduces. For example, we can first design a cosine modulated FB (CMFB) with three channels whose prototype filter has a stopband attenuation of about 40 dB. We can then reuse the solution of this CMFB in the design of a CMFB with 16 384 channels whose prototype filter has a similar stopband attenuation. With our proposed method, we need to reoptimize only 14 parameters to design the CMFB with 16 384 channels.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
Keywords
Filter banks (FBs); filter design; linear-phase filters; transmultiplexers (TMUXs)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-117648 (URN)10.1109/TCSII.2014.2387678 (DOI)000352306200017 ()
Available from: 2015-05-12 Created: 2015-05-06 Last updated: 2017-12-04Bibliographically approved
Wang, Y., Xu, H., Johansson, H., Sun, Z. & Wikner, J. (2015). Digital estimation and compensation method for nonlinearity mismatches in time-interleaved analog-to-digital converters. Digital signal processing (Print), 41, 130-141
Open this publication in new window or tab >>Digital estimation and compensation method for nonlinearity mismatches in time-interleaved analog-to-digital converters
Show others...
2015 (English)In: Digital signal processing (Print), ISSN 1051-2004, E-ISSN 1095-4333, Vol. 41, p. 130-141Article in journal (Refereed) Published
Abstract [en]

Channel mismatches in time-interleaved analog-to-digital converters (TIADCs) typically result in significant degradation of the ADCs dynamic performance. Offset, gain, and timing mismatches have been widely investigated whereas nonlinearity mismatches have not. In this work, we analyze the influence of nonlinearity mismatches by using a polynomial model. As a cost measure we use the signal-to-noise and distortion ratio (SNDR) and then derive a compact formula describing the dependency on nonlinearity mismatches. Based on the spectral characteristics of the TIADCs, we propose a foreground estimation method and a compensation method using a cascaded structure of adders and multipliers. Through behavioral-level simulations, we prove the validity of the derivations and demonstrate that the proposed estimation and compensation method can bring a considerable amount of improvement in the combined TIADCs dynamic performance. The proposed method is efficient assuming that a smooth approximation of the nonlinearity mismatches is sufficient.

Place, publisher, year, edition, pages
Elsevier, 2015
Keywords
Analog-to-digital converters; Digital compensation; Foreground estimation; Hybrid filter banks; Nonlinearity mismatches; Time interleaved
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-118843 (URN)10.1016/j.dsp.2015.03.015 (DOI)000354230700012 ()
Available from: 2015-06-08 Created: 2015-06-04 Last updated: 2018-11-08
Pillai, A. K. & Johansson, H. (2015). Efficient Recovery of Sub-Nyquist Sampled Sparse Multi-Band Signals Using Reconfigurable Multi-Channel Analysis and Modulated Synthesis Filter Banks. IEEE Transactions on Signal Processing, 63(19), 5238-5249
Open this publication in new window or tab >>Efficient Recovery of Sub-Nyquist Sampled Sparse Multi-Band Signals Using Reconfigurable Multi-Channel Analysis and Modulated Synthesis Filter Banks
2015 (English)In: IEEE Transactions on Signal Processing, ISSN 1053-587X, E-ISSN 1941-0476, Vol. 63, no 19, p. 5238-5249Article in journal (Refereed) Published
Abstract [en]

Sub-Nyquist cyclic nonuniform sampling (CNUS) of a sparse multi-band signal generates a nonuniformly sampled signal. Assuming that the corresponding uniformly sampled signal satisfies the Nyquist sampling criterion, the sequence obtained via CNUS can be passed through a reconstructor to recover the missing uniform-grid samples. In order to recover the missing uniform-grid samples, the sequence obtained via CNUS is passed through a reconstructor. At present, these reconstructors have very high design and implementation complexity that offsets the gains obtained due to sub-Nyquist sampling. In this paper, we propose a scheme that reduces the design and implementation complexity of the  reconstructor. In contrast to the existing reconstructors which use only a multi-channel synthesis filter bank (FB), the proposed reconstructor utilizes both analysis and synthesis FBs which makes it feasible to achieve an order-of-magnitude reduction of the complexity. The analysis filters are implemented using polyphase networks whose branches are allpass filters with distinct fractional delays and phase shifts. In order to reduce both the design and the implementation complexity of the  synthesis FB, the synthesis filters are implemented using a cosine-modulated FB. In addition to the reduced complexity of the reconstructor, the proposed multi-channel recovery scheme also supports online reconfigurability which is required in flexible (multi-mode) systems where the user subband locations vary with time.

Place, publisher, year, edition, pages
IEEE, 2015
Keywords
Sub-Nyquist sampling, sparse multi-band signals, reconstruction, nonuniform sampling, time-interleaved analog-to-digital converters, filter banks
National Category
Communication Systems
Identifiers
urn:nbn:se:liu:diva-117824 (URN)10.1109/TSP.2015.2451104 (DOI)000360852200017 ()
Available from: 2015-05-08 Created: 2015-05-08 Last updated: 2017-12-04Bibliographically approved
Johansson, H. & Gustafsson, O. (2015). Filter-Bank Based All-Digital Channelizers and Aggregators for Multi-Standard Video Distribution. In: IEEE International Conference on Digital Signal Processing (DSP), 2015: . Paper presented at IEEE International Conference on Digital Signal Processing (DSP), Singapore, July 21–24, 2015. (pp. 1117-1120). IEEE
Open this publication in new window or tab >>Filter-Bank Based All-Digital Channelizers and Aggregators for Multi-Standard Video Distribution
2015 (English)In: IEEE International Conference on Digital Signal Processing (DSP), 2015, IEEE , 2015, p. 1117-1120Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces all-digital flexible channelizersand aggregators for multi-standard video distribution. The overall problem is to aggregate a number of narrow-band subsignals with different bandwidths (6, 7, or 8 MHz) into one composite wide-band signal. In the proposed scheme, this is carried out through a set of analysis filter banks (FBs), that channelize the subsignals into 1/2-MHz subbands, which subsequently are aggregated through one synthesis FB. In this way, full flexibility with a low computational complexity and maintained quality is enabled. The proposed solution offers orders-of-magnitude complexity reductions as compared with a straightforward alternative. Design examples are included that demonstrate the functionality, flexibility, and efficiency.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-123689 (URN)10.1109/ICDSP.2015.7252052 (DOI)000380506600234 ()978-1-4799-8058-1 (ISBN)
Conference
IEEE International Conference on Digital Signal Processing (DSP), Singapore, July 21–24, 2015.
Available from: 2016-01-08 Created: 2016-01-08 Last updated: 2016-11-14Bibliographically approved
Organisations

Search in DiVA

Show all publications