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Nilsson, Anders
Publications (10 of 20) Show all publications
Nilsson, A., Tell, E. & Liu, D. (2009). An 11 mm(2), 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12 mu m CMOS. In: IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA: Vol 44, number 1. Paper presented at 2008 IEEE International Solid State Circuits Conference, ISSCC; San Francisco, CA; United States (pp. 90-97). IEEE, 44(1)
Open this publication in new window or tab >>An 11 mm(2), 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12 mu m CMOS
2009 (English)In: IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA: Vol 44, number 1, IEEE , 2009, Vol. 44, no 1, p. 90-97Conference paper, Published paper (Refereed)
Abstract [en]

With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm(2) in a 0.12 mu m CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.

Place, publisher, year, edition, pages
IEEE, 2009
Keywords
DSP, WiMAX, DVB, SIMT, OFDM, baseband processor
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16532 (URN)10.1109/JSSC.2008.2007167 (DOI)
Conference
2008 IEEE International Solid State Circuits Conference, ISSCC; San Francisco, CA; United States
Available from: 2009-01-30 Created: 2009-01-30 Last updated: 2014-08-19
Liu, D., Nilsson, A. & Eilert, J. (2009). Bridging Dream and Reality: Programmable Baseband Processors for Software-Defined Radio. IEEE COMMUNICATIONS MAGAZINE, 47(9), 134-140
Open this publication in new window or tab >>Bridging Dream and Reality: Programmable Baseband Processors for Software-Defined Radio
2009 (English)In: IEEE COMMUNICATIONS MAGAZINE, ISSN 0163-6804, Vol. 47, no 9, p. 134-140Article in journal (Refereed) Published
Abstract [en]

A programmable radio baseband signal processor is one of the essential enablers of software-defined radio. As wireless standards evolve, the processing power needed for baseband processing increases dramatically and the underlying hardware needs to cope with various standards or even simultaneously maintaining several radio links. Meanwhile, the maximum power consumption allowed by mobile terminals is still strictly limited. These challenges require both system and architecture level innovations. This article introduces a design methodology for radio baseband processors discussing the challenges and solutions of radio baseband signal processing. The LeoCore architecture is presented here as an example of a baseband processor design aimed at reducing power and silicon cost while maintaining sufficient flexibility.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-20907 (URN)10.1109/MCOM.2009.5277467 (DOI)
Available from: 2009-09-26 Created: 2009-09-25 Last updated: 2014-09-10
Di, W., Eilert, J., Liu, D., Nilsson, A., Tell, E. & Alfredsson, E. (2009). System Architecture for 3GPP LTE Modem Using a Programmable Baseband Processo. In: International Symposium on System-on-Chip (SoC 2009).
Open this publication in new window or tab >>System Architecture for 3GPP LTE Modem Using a Programmable Baseband Processo
Show others...
2009 (English)In: International Symposium on System-on-Chip (SoC 2009), 2009Conference paper, Published paper (Refereed)
Abstract [en]

3G evolution towards HSPA and LTE is ongoing which will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing such as time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier demapping. The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ. This brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-50793 (URN)
Available from: 2009-10-14 Created: 2009-10-14 Last updated: 2009-10-17
Nilsson, A. & Liu, D. (2007). Area efficient fully programmable baseband processors. In: SAMOSVII Workshop; SAMOS, Greece, July 16-19: .
Open this publication in new window or tab >>Area efficient fully programmable baseband processors
2007 (English)In: SAMOSVII Workshop; SAMOS, Greece, July 16-19, 2007Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14520 (URN)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-03-25
Nilsson, A. (2007). Design of programmable multi-standard baseband processors. (Doctoral dissertation). : Institutionen för systemteknik
Open this publication in new window or tab >>Design of programmable multi-standard baseband processors
2007 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Efficient programmable baseband processors are important to enable true multi-standard radio platforms as convergence of mobile communication devices and systems requires multi-standard processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM and CDMA with the same processing device. Programmability can also be used to quickly adapt to new and updated standards within the ever changing wireless communication industry since a pure ASIC solution will not be flexible enough. ASIC solutions for multi-standard baseband processing are also less area efficient than their programmable counterparts since processing resources cannot be efficiently shared between different operations. However, as baseband processing is computationally demanding, traditional DSP architectures cannot be used due to their limited computing capacity. Instead VLIW- and SIMD-based processors are used to provide sufficient computing capacity for baseband applications. The drawback of VLIW-based DSPs is their low power efficiency due to the wide instructions that need to be fetched every clock cycle and their control-path overhead. On the other hand, pure SIMD-based DSPs lack the possibility to perform different concurrent operations. Since memory access power is the dominating part of the power consumption in a processor, other alternatives should be investigated.

In this dissertation a new and unique type of processor architecture has been designed that instead of using the traditional architectures has started from the application requirements with efficiency in mind. The architecture is named ``Single Instruction stream Multiple Tasks'', SIMT in short. The SIMT architecture uses the vector nature of most baseband programs to provide a good trade-off between the flexibility of a VLIW processor and the processing efficiency of a SIMD processor. The contributions of this project are the design and research of key architectural components in the SIMT architecture as well as development of design methodologies. Methodologies for accelerator selection are also presented. Furthermore data dependency control and memory management are studied. Architecture and performance characteristics have also been compared between the SIMT and more traditional processor architectures.

A complete system is demonstrated by the BBP2 baseband processor that has been designed using SIMT technology. The SIMT principle has previously been proven in a small scale in silicon in the BBP1 processor implementing a Wireless LAN transceiver. The second demonstrator chip (BBP2) was manufactured early 2007 and implements a full scale system with multiple SIMD clusters and a controller core supporting multiple threads. It includes enough memory to run symbol processing of DVB-H/T, WiMAX, IEEE 802.11a/b/g and WCDMA, and the silicon area is 11 mm2 in a 0.12 um CMOS technology.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2007. p. 169
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1084
Keywords
DSP, baseband processor, ASIP
National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-8908 (URN)978-91-85715-44-2 (ISBN)
Public defence
2007-06-08, Visionen, B-Huset, 10:15 (English)
Opponent
Supervisors
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2018-01-13
Jiao, H., Nilsson, A., Tell, E. & Liu, D. (2006). MIPS Cost Estimation for OFDM-VBLAST systems. In: WCNC, IEEE Wireless Communications and Networking,2006.
Open this publication in new window or tab >>MIPS Cost Estimation for OFDM-VBLAST systems
2006 (English)In: WCNC, IEEE Wireless Communications and Networking,2006, 2006Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34010 (URN)20371 (Local ID)20371 (Archive number)20371 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Nilsson, A. & Liu, D. (2006). Multi-standard support in SIMT programmable baseband processors. In: SSoCC Swedish System-on-chip Conference,2006.
Open this publication in new window or tab >>Multi-standard support in SIMT programmable baseband processors
2006 (English)In: SSoCC Swedish System-on-chip Conference,2006, 2006Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34009 (URN)20370 (Local ID)20370 (Archive number)20370 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Nilsson, A., Tell, E. & Liu, D. (2006). Simultaneous multistandard support in programmable baseband processors. In: Proceedings of IEEE PRIME 2006, Otranto, Italy: .
Open this publication in new window or tab >>Simultaneous multistandard support in programmable baseband processors
2006 (English)In: Proceedings of IEEE PRIME 2006, Otranto, Italy, 2006Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14521 (URN)
Available from: 2007-05-22 Created: 2007-05-22
Nilsson, A., Tell, E. & Liu, D. (2005). A fully programmable Rake-receiver architecture for multi-standard baseband processors. In: Proceedings of the Intl. conference on Networks and Communication systems, NCS2005: . Paper presented at The Intl. conference on Networks and Communication systems, NCS2005. Krabi, Thailand 2005. (pp. 292-297).
Open this publication in new window or tab >>A fully programmable Rake-receiver architecture for multi-standard baseband processors
2005 (English)In: Proceedings of the Intl. conference on Networks and Communication systems, NCS2005, 2005, p. 292-297Conference paper, Published paper (Other academic)
Abstract [en]

Programmability will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and Maximum Ratio Combining (MRC) based channel equalization for a large number of wireless transmission systems in software. Our processor is based on a programmable DSP processor with SIMD-computing clusters. We also map Rake receiver kernel functions supporting a large number of commonWireless LAN and 3G standards to this microarchitecture. The use of the inherit flexibility for future standards is also discussed. Benchmarking show that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA (FDD/TDD-modes), TD-SCDMA and the higher data rates of IEEE 802.11b (CCK) at clock frequency not exceeding 76 MHz.

Keywords
CDMA, Rake, MRC, DSP, SDR
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14524 (URN)
Conference
The Intl. conference on Networks and Communication systems, NCS2005. Krabi, Thailand 2005.
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2013-11-06
Tell, E., Nilsson, A. & Liu, D. (2005). A Low Area and Low Power Programmable Baseband Processor Architecture. In: International workshop on SoC for real-time applications,2005.
Open this publication in new window or tab >>A Low Area and Low Power Programmable Baseband Processor Architecture
2005 (English)In: International workshop on SoC for real-time applications,2005, 2005Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-29544 (URN)14915 (Local ID)14915 (Archive number)14915 (OAI)
Available from: 2009-10-09 Created: 2009-10-09
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