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Liu, Dake
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Publications (10 of 136) Show all publications
Ul Haque, M. F., Johansson, T. & Liu, D. (2016). Large dynamic range PWM transmitter. In: : . Paper presented at Swedish Microwave Days - GigaHertz and AntennEMB and the GigaHertz Symposium ,15-16 Mars, 2016.Konsert & Kongress Center in Linköping (pp. 34). Linkoping
Open this publication in new window or tab >>Large dynamic range PWM transmitter
2016 (English)Conference paper, Oral presentation with published abstract (Other (popular science, discussion, etc.))
Place, publisher, year, edition, pages
Linkoping: , 2016
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-127998 (URN)
Conference
Swedish Microwave Days - GigaHertz and AntennEMB and the GigaHertz Symposium ,15-16 Mars, 2016.Konsert & Kongress Center in Linköping
Available from: 2016-05-16 Created: 2016-05-16 Last updated: 2016-05-23
Haque, M. F., Johansson, T. & Liu, D. (2015). Combined RF and Multiphase PWM Transmitter. In: 2015 European Conference on Circuit Theory and Design (ECCTD): . Paper presented at 2015 European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, August 24-26, 2015 (pp. 264-267). IEEE
Open this publication in new window or tab >>Combined RF and Multiphase PWM Transmitter
2015 (English)In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 264-267Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents two novel transmitter architectures based on the combination of radio-frequency pulse-width modulation and multiphase pulse-width modulation. The proposed transmitter architectures provide good amplitude resolution and large dynamic range at high carrier frequency, which is problematic with existing radio-frequency pulse-width modulation based transmitters. They also have better power efficiency and smaller chip area compared to multiphase pulse-width modulation based transmitters.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-122703 (URN)10.1109/ECCTD.2015.7299999 (DOI)000380498200001 ()978-1-4799-9877-7 (ISBN)
Conference
2015 European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, August 24-26, 2015
Available from: 2015-11-16 Created: 2015-11-16 Last updated: 2017-01-18Bibliographically approved
Haque, M. F., Johansson, T. & Liu, D. (2015). Combined RF and Multiphase PWM Transmitter. In: : . Paper presented at Swedish System on Chip Conference (SSoCC'15), Göteborg, Sweden, May 4-5 2015.
Open this publication in new window or tab >>Combined RF and Multiphase PWM Transmitter
2015 (English)Conference paper, Published paper (Other academic)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-122711 (URN)
Conference
Swedish System on Chip Conference (SSoCC'15), Göteborg, Sweden, May 4-5 2015
Available from: 2015-11-17 Created: 2015-11-17 Last updated: 2015-11-30Bibliographically approved
Karlsson, A., Sohl, J. & Liu, D. (2015). Cost-efficient Mapping of 3- and 5-point DFTs to General Baseband Processors. In: International Conference on Digital Signal Processing (DSP), Singapore, 21-24 July, 2015: . Paper presented at IEEE International Conference on Digital Signal Processing (DSP) (pp. 780-784). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Cost-efficient Mapping of 3- and 5-point DFTs to General Baseband Processors
2015 (English)In: International Conference on Digital Signal Processing (DSP), Singapore, 21-24 July, 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 780-784Conference paper, Published paper (Refereed)
Abstract [en]

Discrete Fourier transforms of 3 and 5 points are essential building blocks in FFT implementations for standards such as 3GPP-LTE. In addition to being more complex than 2 and 4 point DFTs, these DFTs also cause problems with data access in SDR-DSPs, since the data access width, in general, is a power of 2. This work derives mappings of these DFTs to a 4-way SIMD datapath that has been designed with 2 and 4-point DFT in mind. Our instruction set proposals, based on modified Winograd DFT, achieves single cycle execution of 3-point DFTs and 2.25 cycle average execution of 5-point DFTs in a cost-effective manner by reutilizing the already available arithmetic units. This represents an approximate speed-up of 3 times compared to an SDR-DSP with only MAC-support. In contrast to our more general design, we also demonstrate that a typical single-purpose FFT-specialized 5-way architecture only delivers 9% to 25% extra performance on average, while requiring 85% more arithmetic units and a more expensive memory subsystem.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-120397 (URN)10.1109/ICDSP.2015.7251982 (DOI)000380506600164 ()978-1-4799-8058-1 (ISBN)
Conference
IEEE International Conference on Digital Signal Processing (DSP)
Projects
HiPEC
Available from: 2015-08-04 Created: 2015-08-04 Last updated: 2018-01-11
Liu, D., Wang, Z. & Luo, L. (2015). Editorial Material: SPECIAL ISSUE ON COMMUNICATION IC in CHINA COMMUNICATIONS, vol 12, issue 5, pp III-VI. China Communications, 12(5), III-VI
Open this publication in new window or tab >>Editorial Material: SPECIAL ISSUE ON COMMUNICATION IC in CHINA COMMUNICATIONS, vol 12, issue 5, pp III-VI
2015 (English)In: China Communications, ISSN 1673-5447, Vol. 12, no 5, p. III-VIArticle in journal, Editorial material (Other academic) Published
Abstract [en]

n/a

Place, publisher, year, edition, pages
CHINA INST COMMUNICATIONS, 2015
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-119283 (URN)000354386100001 ()
Available from: 2015-06-12 Created: 2015-06-12 Last updated: 2017-12-04
Karlsson, A., Sohl, J. & Liu, D. (2015). Energy-efficient sorting with the distributed memory architecture ePUMA. In: IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA): . Paper presented at IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA) (pp. 116-123). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Energy-efficient sorting with the distributed memory architecture ePUMA
2015 (English)In: IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 116-123Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the novel heterogeneous DSP architecture ePUMA and demonstrates its features through an implementation of sorting of larger data sets. We derive a sorting algorithm with fixed-size merging tasks suitable for distributed memory architectures, which allows very simple scheduling and predictable data-independent sorting time.The implementation on ePUMA utilizes the architecture's specialized compute cores and control cores, and local memory parallelism, to separate and overlap sorting with data access and control for close to stall-free sorting.Penalty-free unaligned and out-of-order local memory access is used in combination with proposed application-specific sorting instructions to derive highly efficient local sorting and merging kernels used by the system-level algorithm.Our evaluation shows that the proposed implementation can rival the sorting performance of high-performance commercial CPUs and GPUs, with two orders of magnitude higher energy efficiency, which would allow high-performance sorting on low-power devices.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-120398 (URN)10.1109/Trustcom.2015.620 (DOI)000380431400015 ()978-1-4673-7952-6 (ISBN)
Conference
IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)
Projects
HiPEC
Available from: 2015-08-04 Created: 2015-08-04 Last updated: 2018-01-11
Karlsson, A., Sohl, J. & Liu, D. (2015). ePUMA: A Processor Architecture for Future DSP. In: International Conference on Digital Signal Processing (DSP), Singapore, 21-24 July, 2015: . Paper presented at IEEE International Conference on Digital Signal Processing (DSP) (pp. 253-257).
Open this publication in new window or tab >>ePUMA: A Processor Architecture for Future DSP
2015 (English)In: International Conference on Digital Signal Processing (DSP), Singapore, 21-24 July, 2015, 2015, p. 253-257Conference paper, Published paper (Refereed)
Abstract [en]

Since the breakdown of Dennard scaling the primary design goal for processor designs has shifted from increasing performance to increasing performance per Watt. The ePUMA platform is a flexible and configurable DSP platform that tries to address many of the problems with traditional DSP designs, to increase  performance, but use less power. We trade the flexibility of traditional VLIW DSP designs for a simpler single instruction issue scheme and instead make sure that each instruction can perform more work. Multi-cycle instructions can operate directly on vectors and matrices in memory and the datapaths implement common DSP subgraphs directly in hardware, for high compute throughput. Memory bottlenecks, that are common in other architectures, are handled with flexible LUT-based multi-bank memory addressing and memory parallelism. A major contributor to energy consumption, data movement, is reduced by using heterogeneous interconnect and clustering compute resources around local memories for simple data sharing. To evaluate ePUMA we have implemented the majority of the kernel library from a commercial VLIW DSP manufacturer for comparison. Our results not only show good performance, but also an order of magnitude increase in energy- and area efficiency. In addition, the kernel code size is reduced by 91% on average compared to the VLIW DSP. These benefits makes ePUMA an attractive solution for future DSP.

National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-120396 (URN)10.1109/ICDSP.2015.7251870 (DOI)000380506600052 ()978-1-4799-8058-1 (ISBN)
Conference
IEEE International Conference on Digital Signal Processing (DSP)
Projects
HiPEC
Available from: 2015-08-04 Created: 2015-08-04 Last updated: 2018-01-11
Wu, Z. & Liu, D. (2015). High-Throughput Trellis Processor for Multistandard FEC Decoding. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 23(12), 2757-2767
Open this publication in new window or tab >>High-Throughput Trellis Processor for Multistandard FEC Decoding
2015 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 23, no 12, p. 2757-2767Article in journal (Refereed) Published
Abstract [en]

Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASIP) is presented for multistandard trellis decoding. A unified forward-backward recursion kernel with an eight-state parallel trellis structure is proposed. Based on the kernel, a datapath for multialgorithm and a shared memory subsystem are introduced. The flexibility and the compatibility are guaranteed by a programmable decoding flow and the trellis decoding instruction set. Synthesis results show that the area consumption is 2.12 mm(2) (65 nm). TASIP provides trimode FEC decoding ability with the throughput of 533, 186, and 225 Mb/s for LDPC, turbo, and 64 states CC under the clock frequency of 200 MHz, which outperforms other trimode proposals both in area efficiency and recursion efficiency. TASIP provides high-throughput decoding for current standards, including 3rd Generation Partnership Project-Long Term Evolution, 802.16e, and 802.11n, with unified architecture and high compatibility.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2015
Keywords
Application-specific instruction-set processor (ASIP); forward-backward recursion (FBR); multistandard forward error correction (FEC); single instruction multiple data (SIMD); trellis decoding
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-123513 (URN)10.1109/TVLSI.2014.2382108 (DOI)000365206300001 ()
Note

Funding Agencies|National High-Tech Research and Development Program (863 Program) of China [2014AA01A705]

Available from: 2015-12-22 Created: 2015-12-21 Last updated: 2017-12-01Bibliographically approved
Haque, M. F., Johansson, T. & Liu, D. (2015). Modified Band-limited Pulse-Width Modulated Polar Transmitter. In: : . Paper presented at 15th International Symposium on Microwave and Optical Technology (ISMOT 2015), Dresden, Germany, June 29-July 1 2015.
Open this publication in new window or tab >>Modified Band-limited Pulse-Width Modulated Polar Transmitter
2015 (English)Conference paper, Published paper (Other academic)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-122702 (URN)
Conference
15th International Symposium on Microwave and Optical Technology (ISMOT 2015), Dresden, Germany, June 29-July 1 2015
Available from: 2015-11-16 Created: 2015-11-16 Last updated: 2015-11-30Bibliographically approved
Ul Haque, M. F., Johansson, T. & Liu, D. (2015). Power Efficienct Band-limited Pulse Width Modulated Transmitter. In: : . Paper presented at Swedish System on Chip Conference (SSoCC 2015) in Goteborg. 4-5 maj 2015, Novotel Hotel, Göteborg. Gothenburg
Open this publication in new window or tab >>Power Efficienct Band-limited Pulse Width Modulated Transmitter
2015 (English)Conference paper, Oral presentation only (Other (popular science, discussion, etc.))
Place, publisher, year, edition, pages
Gothenburg: , 2015
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-127999 (URN)
Conference
Swedish System on Chip Conference (SSoCC 2015) in Goteborg. 4-5 maj 2015, Novotel Hotel, Göteborg
Available from: 2016-05-16 Created: 2016-05-16 Last updated: 2016-05-23
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