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Publications (10 of 26) Show all publications
Ehliar, A. (2014). Area Efficient Floating-Point Adder and Multiplier with IEEE-754 Compatible Semantics. In: : . Paper presented at ICFPT2014: The 2014 International Conference on Field-Programmable Technology.
Open this publication in new window or tab >>Area Efficient Floating-Point Adder and Multiplier with IEEE-754 Compatible Semantics
2014 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we describe an open source floating-point adder andmultiplier implemented using a 36-bit custom number format based onradix-16 and optimized for the 7-series FPGAs from Xilinx. Althoughthis number format is not identical to the single-precision IEEE-754format, the floating-point operators are designed in such a way thatthe numerical results for a given operation will be identical to theresult from an IEEE-754 compliant operator with support forround-to-nearest even, NaNs and Infs, and subnormalnumbers. The drawback of this number format is that the rounding stepis more involved than in a regular, radix-2 based operator. On theother hand, the use of a high radix means that the area costassociated with normalization and denormalization can be reduced,leading to a net area advantage for the custom number format, underthe assumption that support for subnormal numbers is required.

The area of the floating-point adder in a Kintex-7 FPGA is 261 sliceLUTs and the area of the floating-point multiplier is 235 slice LUTsand 2 DSP48E blocks. The adder can operate at 319 MHz and themultiplier can operate at a frequency of 305 MHz.

National Category
Embedded Systems
Identifiers
urn:nbn:se:liu:diva-114322 (URN)
Conference
ICFPT2014: The 2014 International Conference on Field-Programmable Technology
Available from: 2015-02-18 Created: 2015-02-18 Last updated: 2015-02-18Bibliographically approved
Garrido, M., Acevedo, M., Ehliar, A. & Gustafsson, O. (2014). Challenging the Limits of FFT Performance on FPGAs. In: : . Paper presented at 2014 International Symposium on Integrated Circuits (ISIC) 10-12 December 2014 Singapore (pp. 172-175). IEEE
Open this publication in new window or tab >>Challenging the Limits of FFT Performance on FPGAs
2014 (English)Conference paper, Published paper (Refereed)
Abstract [en]

This paper analyzes the limits of FFT performance on FPGAs. For this purpose, a FFT generation tool has been developed. This tool is highly parameterizable and allows for generating FFTs with different FFT sizes and amount of parallelization. Experimental results for FFT sizes from 16 to 65536, and 4 to 64 parallel samples have been obtained. They show that even the largest FFT architectures fit well in today's FPGAs, achieving throughput rates from several GSamples/s to tens of GSamples/s.

Place, publisher, year, edition, pages
IEEE, 2014
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-127974 (URN)10.1109/ISICIR.2014.7029571 (DOI)978-1-4799-4833-8 (ISBN)
Conference
2014 International Symposium on Integrated Circuits (ISIC) 10-12 December 2014 Singapore
Available from: 2016-05-13 Created: 2016-05-13 Last updated: 2016-06-10Bibliographically approved
Gustafsson, O. & Ehliar, A. (2013). Low-complexity general FIR filters based on Winograd's inner product algorithm. Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China. IEEE conference proceedings
Open this publication in new window or tab >>Low-complexity general FIR filters based on Winograd's inner product algorithm
2013 (English)Conference paper, Published paper (Other academic)
Place, publisher, year, edition, pages
IEEE conference proceedings, 2013
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-86748 (URN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
Available from: 2013-01-03 Created: 2013-01-03 Last updated: 2015-03-11
Gustavsson, M., Ul Amin, F., Bjorklid, A., Ehliar, A., Xu, C. & Svensson, C. (2012). A High-Rate Energy-Resolving Photon-Counting ASIC for Spectral Computed Tomography. IEEE Transactions on Nuclear Science, 59(1), 30-39
Open this publication in new window or tab >>A High-Rate Energy-Resolving Photon-Counting ASIC for Spectral Computed Tomography
Show others...
2012 (English)In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 59, no 1, p. 30-39Article in journal (Refereed) Published
Abstract [en]

We describe a high-rate energy-resolving photon-counting ASIC aimed for spectral computed tomography. The chip has 160 channels and 8 energy bins per channel. It demonstrates a noise level of ENC= electrons at 5 pF input load at a power consumption of andlt;5mW/channel. Maximum count rate is 17 Mcps at a peak time of 40 ns, made possible through a new filter reset scheme, and maximum read-out frame rate is 37 kframe/s.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2012
Keywords
CMOS, photon counting, spectral computed tomography, x-ray detection
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-75723 (URN)10.1109/TNS.2011.2169811 (DOI)000300422500005 ()
Note
Funding Agencies|Erling-Persson family foundation (Familjen Erling-Perssons stiftelse)||Available from: 2012-03-09 Created: 2012-03-09 Last updated: 2017-12-07
Ehliar, A. (2012). EBRAM - Extending the BlockRAMs in FPGAs to support caches and hash tables inan efficient manner. In: : . Paper presented at IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, April 29 - May 1 2012, Toronto, ON, Canada (pp. 242-242). IEEE Computer Society
Open this publication in new window or tab >>EBRAM - Extending the BlockRAMs in FPGAs to support caches and hash tables inan efficient manner
2012 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we discuss how a typical Block RAM in an FPGA can be extended to enable the implementation of more efficient caches in FPGAs with very minor modifications to the existing Block RAM architectures. In addition, the modifications also allow other components, such as hash tables, to be implemented more efficiently.

Place, publisher, year, edition, pages
IEEE Computer Society, 2012
Keywords
Cache, FPGA, BlockRAM
National Category
Embedded Systems
Identifiers
urn:nbn:se:liu:diva-80348 (URN)10.1109/FCCM.2012.52 (DOI)000309191400041 ()978-1-4673-1605-7 (ISBN)
Conference
IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, April 29 - May 1 2012, Toronto, ON, Canada
Available from: 2012-08-23 Created: 2012-08-23 Last updated: 2015-02-18
Ehliar, A. & Siverskog, J. (2011). Using Partial Reconfigurability to aid Debugging of FPGA Designs. Paper presented at VII Southern Conference on Programmable Logic (SPL).
Open this publication in new window or tab >>Using Partial Reconfigurability to aid Debugging of FPGA Designs
2011 (English)Conference paper, Published paper (Refereed)
Abstract [en]

This paper discusses the use of partial reconfigurability in Xilinx FPGA designs in order to aid debugging. A debugging framework is proposed where the use of partial reconfigurability can allow for added flexibility by allowing a debugger to decide at run time what debugging module to use. This paper also presents an open source debugging tool which allows a user to read-out the contents of memory blocks in Xilinx designs without needing to use any JTAG adapter. This allows a user to debug an FPGA in situations which would otherwise be difficult, i.e. in the field.

National Category
Embedded Systems
Identifiers
urn:nbn:se:liu:diva-72273 (URN)10.1109/SPL.2011.5782651 (DOI)
Conference
VII Southern Conference on Programmable Logic (SPL)
Available from: 2011-11-24 Created: 2011-11-24 Last updated: 2015-02-18
Ehliar, A. (2010). Optimizing Xilinx designs through primitive instantiation. In: FPGAworld '10 Proceedings of the 7th FPGAworld Conference. Paper presented at 7th FPGAworld Conference (pp. 20-27). New York: ACM
Open this publication in new window or tab >>Optimizing Xilinx designs through primitive instantiation
2010 (English)In: FPGAworld '10 Proceedings of the 7th FPGAworld Conference, New York: ACM , 2010, p. 20-27Conference paper, Published paper (Refereed)
Abstract [en]

This paper is intended as a guideline for people who are interested in manual instantiation of FPGA primitives as a way of improving the performance of an FPGA design. The focus of the paper is on designs where slice primitives like flip-fops and lookup tables are instantiated. Guidelines on how to develop a design with manual instantiation are presented together with a case study of a high performance bitserial two's complement divider where a majority of the area is manually instantiated. This divider is capable of reaching a maximum frequency of 345 MHz in the fastest Virtex-4 while utilizing less than 150 LUTs thanks to the high amount of manual optimizations. An open source library containing modules intended to promote the structured development of modules with manually instantiated components is also presented.

Place, publisher, year, edition, pages
New York: ACM, 2010
Keywords
FPGA, Primitive instantiation. Bit-serial divider, carry-chain
National Category
Embedded Systems
Identifiers
urn:nbn:se:liu:diva-72274 (URN)10.1145/1975482.1975484 (DOI)978-1-4503-0481-8 (ISBN)
Conference
7th FPGAworld Conference
Available from: 2011-11-24 Created: 2011-11-24 Last updated: 2015-02-18
Ehliar, A. & Liu, D. (2009). An Asic Perspective on FPGA Optimizations. In: 19th International Conference on Field Programmable Logic and Applications (FPL): . Paper presented at FPL 09: 19th International Conference on Field Programmable Logic and Applications; Prague; Czech Republic (pp. 218-223).
Open this publication in new window or tab >>An Asic Perspective on FPGA Optimizations
2009 (English)In: 19th International Conference on Field Programmable Logic and Applications (FPL), 2009, p. 218-223Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect the performance and area of an ASIC port. We find that most techniques that are used to optimize a design for an FPGA will not have a negative impact on the area in an ASIC. The intended audience for this paper are engineers charged with creating designs or IP cores that are optimized for both FPGAs and ASICs.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-50674 (URN)10.1109/FPL.2009.5272311 (DOI)000277506300033 ()978-1-4244-3892-1 (ISBN)978-1-4244-3892-1 (ISBN)
Conference
FPL 09: 19th International Conference on Field Programmable Logic and Applications; Prague; Czech Republic
Available from: 2009-10-13 Created: 2009-10-13 Last updated: 2015-02-18
Ehliar, A. & Liu, D. (2009). An ASIC Perspective on High Performance FPGA Design. In: : .
Open this publication in new window or tab >>An ASIC Perspective on High Performance FPGA Design
2009 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect the performance and area of an ASIC port. We find that most techniques that are used to optimize a design for an FPGA will not have a negative impact on the area in an ASIC. The intended audience for this paper are engineers charged with creating designs or IP cores that are optimized for both FPGAs and ASICs.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16564 (URN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
Ehliar, A. (2009). Performance driven FPGA design with an ASIC perspective. (Doctoral dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Performance driven FPGA design with an ASIC perspective
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient.

This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA.

Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA.

The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated.

All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs.

Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2009. p. 165
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1237
Keywords
FPGA Optimizations, ASIC and FPGA codesign
National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-16372 (URN)978-91-7393-702-3 (ISBN)
Public defence
2009-02-27, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2009-02-02 Created: 2009-01-19 Last updated: 2018-01-13Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-0111-2384

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