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Karlström, Per
Alternative names
Publications (10 of 10) Show all publications
Karlström, P., Zhou, W. & Liu, D. (2010). Automatic Assembler Generator for NoGAP. In: Ph.D. Research in Microelectronics and Electronics. Paper presented at Ph.D. Research in Microelectronics and Electronics.
Open this publication in new window or tab >>Automatic Assembler Generator for NoGAP
2010 (English)In: Ph.D. Research in Microelectronics and Electronics, 2010Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-58301 (URN)
Conference
Ph.D. Research in Microelectronics and Electronics
Available from: 2010-08-09 Created: 2010-08-09 Last updated: 2010-08-27
Karlström, P., Zhou, W. & Liu, D. (2010). Automatic Port and Bus Sizing in NoGAP. In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation: . Paper presented at SAMOS X: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (pp. 258-264).
Open this publication in new window or tab >>Automatic Port and Bus Sizing in NoGAP
2010 (English)In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2010, p. 258-264Conference paper, Published paper (Refereed)
Abstract [en]

ASIP processors and programmable accelerators are replacing monolithic ASICs in more and more areas. However the design and implementation of a new ASIP processor or programmable accelerator requires a substantial design effort. There are a number of existing tools that promise to ease this design effort, but using these tools usually means that the designer get locked into the tools a priori assumtions and it is therefore hard to develop truly novel ASIPs or accelerators. NoGAP is a tool that delivers design support while not locking the designer into any predefined template architecture. An important aspect of NoGAPs design process is the ability to design the data path of each instruction individually. Therefore the size of input/output ports can sometimes not be known while designing the individual functional units. For this reason we have introduced the concept of dynamic port sizes, which is an extension of the parameter/generic concept in Verilog/VHDL. A problem arises if the data path graph contains loops, either due to intra or inter instruction dependencies. This paper will present the algorithm used to solve this looping problem.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-58302 (URN)10.1109/ICSAMOS.2010.5642057 (DOI)978-1-4244-7938-2 (ISBN)978-1-4244-7936-8 (ISBN)
Conference
SAMOS X: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
Available from: 2010-08-09 Created: 2010-08-09 Last updated: 2014-09-19
Karlström, P. A. (2010). NoGAP: Novel Generator of Accelerators and Processors. (Doctoral dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>NoGAP: Novel Generator of Accelerators and Processors
2010 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

ASIPs are needed to handle the future demand of flexible yet highperformance embedded computing. The flexibility of ASIPs makes them preferable over fixed function ASICs. Also, a well designed ASIP, has a power consumption comparable to ASICs.  However the cost associated with ASIP design is a limiting factor for a more wide spread adoption. A number of different tools have been proposed, promising to ease this design process. However all of the current state of the art tools limits the designer due to a template based design process. It blocks design freedoms and limits the I/O bandwidth of the template. We have therefore proposed the Novel Generator of Accelerator and Processors (NoGAP). NoGAP is a design automation tool for ASIP andaccelerator design that puts very few limits on what can be designed, yet NoGAP gives support by automating much of the tedious anderror prone tasks associated with ASIP design.

This thesis will present NoGAP and much of its key concepts. Such as; the NoGAP-CL) which is a language used to implement processors in NoGAP, This thesis exposes NoGAP's key technologies, which include automatic bus and wire sizing, instruction decoder and pipeline management, how PC-FSMs can be generated, how an assembler can be generated, and how cycle accurate simulators can be generated.

We have so far proven NoGAP's strengths in three extensive case studies, in one a floating point pipelined data path was designed, in another a simple RISC processor was designed, and finally one advanced RISC style DSP was designed using NoGAP. All these case studies points to the same conclusion, that NoGAP speeds up development time, clarify complex pipeline architectures, retains design flexibility, and most importantly does not incur much performance penalty, compared to hand optimized RTL code.

We belive that the work presented in this thesis shows that NoGAP, using our proposed novel approach to micro architecture design, can have a significant impact on both academic and industrial hardware design. To our best knowledge NoGAP is the first system that has demonstrated that a template free processor construction framework can be developed and generate high performance hardware solutions.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2010. p. 274
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1347
Keywords
ADL, ESL, Processor, Accelerator, Compiler
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering Computer Engineering
Identifiers
urn:nbn:se:liu:diva-60192 (URN)978-91-7393-293-6 (ISBN)
Public defence
2010-11-26, Visionen, Hus B,, Campus Valla, Linköping University, Linköping, 10:00 (English)
Opponent
Supervisors
Projects
NoGAP
Available from: 2010-11-17 Created: 2010-10-07 Last updated: 2018-01-12Bibliographically approved
Zhou, W., Karlström, P. & Liu, D. (2010). NoGapCL: A flexible common language for processor hardware description. Paper presented at The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.
Open this publication in new window or tab >>NoGapCL: A flexible common language for processor hardware description
2010 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. NoGap (Novel Generator of Micro Architecture and Processor) is a tool for ASIP designs, utilizing hardware multiplexed data paths. One of the main advantages of NoGap compared to other EDA tools for processor design, is that NoGap impose few limits on the architecture and thus design freedom. NoGap does not assume a fixed processor template and is not a data flow synthesizer. To reach this flexibility NoGap makes heavy use of the compositional design principle. This paper describe NoGapCL, a flexible common language for processor hardware description. A RISC processor using NoGapCL has been constructed with NoGap in less than a working day and synthesized to an FPGA. With no FPGA specific optimizations this processor met timing closure at 178MHz in a Virtex-4 LX80 speedgrade 12.

Keywords
ADL, ASIP, CAD
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-58303 (URN)10.1109/DDECS.2010.5491778 (DOI)978-1-4244-6612-2 (ISBN)
Conference
The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Available from: 2010-08-09 Created: 2010-08-09 Last updated: 2010-08-27
Karlström, P., Zhou, W. & Liu, D. (2010). Operation Classification for Control Path Synthetization with NoGAP. In: : . Paper presented at Seventh International Conference on Information Technology (pp. 1195-1200).
Open this publication in new window or tab >>Operation Classification for Control Path Synthetization with NoGAP
2010 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. NoGAP (Novel Generator of Micro Architecture and Processor) is a tool for ASIP designs utilizing hardware multiplexed data paths. One of the main advantages of NoGAP compared to other ADL tools is that it does not impose limits on the architecture and thus design freedom. NoGAP does not assume a fixed processor template and is not another data flow synthesizer. To reach this flexibility NoGAP makes heavy use of the compositional design principle and is therefore divided into three parts Mage, Mase, and Castle. This paper discusses the techniques used in NoGAP for control path synthetization. A RISC processor has been constructed with NoGAP in less than a working day and synthesized to an FPGA. With no FPGA specific optimizations this processor met timing closure at 178MHz in a Virtex-4 LX80 speedgrade 12.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-58300 (URN)10.1109/ITNG.2010.142 (DOI)978-1-4244-6270-4 (ISBN)
Conference
Seventh International Conference on Information Technology
Available from: 2010-08-09 Created: 2010-08-09 Last updated: 2014-09-30
Karlström, P. & Liu, D. (2009). NoGAP: A Micro Architecture Construction Framework (1ed.). In: Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong (Ed.), Embedded Computer Systems: Architectures, Modeling, and Simulation: 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings. Paper presented at 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009 (pp. 171-180). Berlin: Springer Berlin/Heidelberg
Open this publication in new window or tab >>NoGAP: A Micro Architecture Construction Framework
2009 (English)In: Embedded Computer Systems: Architectures, Modeling, and Simulation: 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings / [ed] Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong, Berlin: Springer Berlin/Heidelberg, 2009, 1, p. 171-180Conference paper, Published paper (Refereed)
Abstract [en]

Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a vide variety of fields. However the design of an ASIP is today a substantial design effort. This paper discusses NoGAP (Novel Generator for ASIP) a tool for ASIP designs utilizing hardware multiplexed data paths. One of the main advantages of NoGAP compared to other ADL tools is that it does not impose limits on the architecture and thus design freedom. To reach this flexibility NoGAP makes heavy use of the compositional design principle and is therefore divided into three parts Mage, Mase, and Castle. This paper presents the central concepts of NoGAP to show that it is possible to reach this advertised flexibility and still be able to generate HDL code and tools such as simulators and assemblers.

Place, publisher, year, edition, pages
Berlin: Springer Berlin/Heidelberg, 2009 Edition: 1
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 5657
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-50802 (URN)10.1007/978-3-642-03138-0_18 (DOI)978-3-642-03137-3 (ISBN)978-3-642-03138-0 (ISBN)
Conference
9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009
Projects
NoGAP
Available from: 2012-05-30 Created: 2009-10-14 Last updated: 2018-01-26Bibliographically approved
Ehliar, A., Karlström, P. & Liu, D. (2008). A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA. In: International Conference on Field Programmable Logic and Applications FLP 2008, Heidelberg, Germany, 2008: (pp. 599-602).
Open this publication in new window or tab >>A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
2008 (English)In: International Conference on Field Programmable Logic and Applications FLP 2008, Heidelberg, Germany, 2008, 2008, p. 599-602Conference paper, Published paper (Refereed)
Abstract [en]

As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity down and this paper shows how this can be done while retaining sufficient functionality for a high performance processor.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16562 (URN)10.1109/FPL.2008.4630018 (DOI)978-1-4244-1960-9 (ISBN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
Karlström, P., Ehliar, A. & Liu, D. (2008). High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. IET Computers and digital techniques, 2, 305-313
Open this publication in new window or tab >>High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
2008 (English)In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, p. 305-313Article in journal (Refereed) Published
Abstract [en]

There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12).

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16563 (URN)10.1049/iet-cdt:20070075 (DOI)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
Karlström, P., Ehliar, A. & Liu, D. (2006). High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4. In: NORCHIP 2006: The Nordic Microelectronics Event. 2006: . Paper presented at 24th Norchip Conference, 20-21 November 2006, Linkoping, Sweden. (pp. 31-34).
Open this publication in new window or tab >>High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4
2006 (English)In: NORCHIP 2006: The Nordic Microelectronics Event. 2006, 2006, p. 31-34Conference paper, Published paper (Refereed)
Abstract [en]

Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-100922 (URN)10.1109/NORCHP.2006.329238 (DOI)9781424407729 (ISBN)
Conference
24th Norchip Conference, 20-21 November 2006, Linkoping, Sweden.
Available from: 2013-11-14 Created: 2013-11-14 Last updated: 2015-02-18
Wu, D., Karlström, P., Eilert, J., Ehliar, A. & Liu, D. (2006). Media DSP: An Application Specific Heterogeneous Multiprocessor SoC. In: SSoCC Swedish System-on-Chip Conference,2006.
Open this publication in new window or tab >>Media DSP: An Application Specific Heterogeneous Multiprocessor SoC
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2006 (English)In: SSoCC Swedish System-on-Chip Conference,2006, 2006Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33993 (URN)20271 (Local ID)20271 (Archive number)20271 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-02-18
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