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Johansson, Kenny
Publications (10 of 37) Show all publications
Johansson, K., Gustafsson, O. & DeBrunner, L. (2009). Estimation of the switching activity in shift-and-add based computations. In: IEEE International Symposium on Circuits and Systems (pp. 3054-3057). Piscataway
Open this publication in new window or tab >>Estimation of the switching activity in shift-and-add based computations
2009 (English)In: IEEE International Symposium on Circuits and Systems, Piscataway, 2009, p. 3054-3057Conference paper, Published paper (Refereed)
Abstract [en]

In this work, we propose a switching activity model for constant multipliers. The model can also be used for other architectures that are composed by full adders. Hence, the proposed model is suitable to be used in power consumption aware design algorithms. An important category is algorithms for the multiple-constant multiplication (MCM) problem. The model is shown to agree well with simulations, especially for carry-save arithmetic.

Place, publisher, year, edition, pages
Piscataway: , 2009
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-51069 (URN)10.1109/ISCAS.2009.5118447 (DOI)000275929801450 ()978-1-4244-3827-3 (ISBN)
Available from: 2009-10-15 Created: 2009-10-15 Last updated: 2015-03-11
Gustafsson, O. & Johansson, K. (2008). An empirical study on standard cell synthesis of elementary function look-up tables. In: Conference Record - Asilomar Conference on Signals, Systems and Computers: . Paper presented at Asilomar Conference on Signals, Systems, and Computers,2008 (pp. 1810-1813). Piscataway, NJ: IEEE
Open this publication in new window or tab >>An empirical study on standard cell synthesis of elementary function look-up tables
2008 (English)In: Conference Record - Asilomar Conference on Signals, Systems and Computers, Piscataway, NJ: IEEE , 2008, p. 1810-1813Conference paper, Published paper (Refereed)
Abstract [en]

When hardware for implementing elementary functions is discussed it is often stated that for "small enough" tables it is possible to just synthesize the HDL description to standard cells. In this work we investigate this fact and show that the resulting cell area primarily depends on the smallest of the number of input and output bits, while the contribution of the larger of the two bit-widths is significantly smaller.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE, 2008
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-44138 (URN)10.1109/ACSSC.2008.5074739 (DOI)000274551001127 ()75783 (Local ID)978-1-4244-2941-7 (ISBN)978-1-4244-2940-0 (ISBN)75783 (Archive number)75783 (OAI)
Conference
Asilomar Conference on Signals, Systems, and Computers,2008
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11
Abbas, M., Qureshi, F., Ullah Sheikh, Z., Gustafsson, O., Johansson, H. & Johansson, K. (2008). Comparison of Multiplierless Implementation of Nonlinear-Phase Versus Linear-Phase FIR filters. Paper presented at 42ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, ISSN 1058-6393. IEEE
Open this publication in new window or tab >>Comparison of Multiplierless Implementation of Nonlinear-Phase Versus Linear-Phase FIR filters
Show others...
2008 (English)Conference paper, Published paper (Refereed)
Abstract [en]

FIR filters are often used because of their linear-phase response. However, there are certain applications where the linear-phase property is not required, such as signal energy estimation, but IIR filters can not be used due to the limitation of sample rate imposed by the recursive algorithm. In this work, we discuss multiplierless implementation of minimum order, and therefore nonlinear-phase, FIR filters and compare it to the linear-phase counterpart.

Place, publisher, year, edition, pages
IEEE, 2008
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-54167 (URN)10.1109/ACSSC.2008.5074475 (DOI)000274551000114 ()978-1-4244-2940-0 (ISBN)
Conference
42ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, ISSN 1058-6393
Available from: 2011-09-20 Created: 2010-02-26 Last updated: 2015-03-11Bibliographically approved
Johansson, K., Gustafsson, O. & Wanhammar, L. (2008). Implementation of elementary functions for logarithmic number systems. IET Computers and digital techniques, 2(4), 295-304
Open this publication in new window or tab >>Implementation of elementary functions for logarithmic number systems
2008 (English)In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, no 4, p. 295-304Article in journal (Refereed) Published
Abstract [en]

 Computations in logarithmic number systems require realisations of four different elementary functions. In the current paper the authors use a recently proposed approximation method based on weighted sums of bit-products to realise these functions. It is shown that the considered method can be used to efficiently realise the different functions. Furthermore, a transformation is proposed to improve the results for functions with logarithmic characteristics. Implementation results shows that significant savings in area and power can be obtained using optimisation techniques. 

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-44129 (URN)10.1049/iet-cdt:20070080 (DOI)75759 (Local ID)75759 (Archive number)75759 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11
Johansson, K. (2008). Low Power and Low Complexity Shift-and-Add Based Computations. (Doctoral dissertation). Linköping University: Linköping University Electronic Press
Open this publication in new window or tab >>Low Power and Low Complexity Shift-and-Add Based Computations
2008 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplications, which are realized using shift-and-add based computations. The possibilities to reduce the complexity, i.e., the chip area, and the energy consumption are investigated. Both serial and parallel arithmetic are considered. The main difference, which is of interest here, is that shift operations in serial arithmetic require flip-flops, while shifts can be hardwired in parallel arithmetic.The possible ways to connect a given number of adders is limited. Thus, for single-constant multiplication, the number of shift-and-add structures is finite. We show that it is possible to save both adders and shifts compared to traditional multipliers. Two algorithms for multiple-constant multiplication using serial arithmetic are proposed. For both algorithms, the total complexity is decreased compared to one of the best-known algorithms designed for parallel arithmetic. Furthermore, the impact of the digit-size, i.e., the number of bits to be processed in parallel, is studied for FIR filters implemented using serial arithmetic. Case studies indicate that the minimum energy consumption per sample is often obtained for a digit-size of around four bits.The energy consumption is proportional to the switching activity, i.e., the average number of transitions between the two logic levels per clock cycle. To achieve low power designs, it is necessary to develop accurate high-level models that can be used to estimate the switching activity. A method for computing the switching activity in bit-serial constant multipliers is proposed.For parallel arithmetic, a detailed complexity model for constant multiplication is introduced. The model counts the required number of full and half adder cells. It is shown that the complexity can be significantly reduced by considering the interconnection between the adders. A main factor for energy consumption in constant multipliers is the adder depth, i.e., the number of cascaded adders. The reason for this is that the switching activity will increase when glitches are propagated to subsequent adders. We propose an algorithm, where all multiplier coefficients are guaranteed to be realized at the theoretically lowest depth possible. Implementation examples show that the energy consumption is significantly reduced using this algorithm compared to solutions with fewer word level adders.For most applications, the input data are correlated since real world signals are processed. A data dependent switching activity model is derived for ripple-carry adders. Furthermore, a switching activity model for the single adder multiplier is proposed. This is a good starting point for accurate modeling of shift-and-add based computations using more adders.Finally, a method to rewrite an arbitrary function as a sum of weighted bit-products is presented. It is shown that for many elementary functions, a majority of the bit-products can be neglected while still maintaining reasonable high accuracy, since the weights are significantly smaller than the allowed error. The function approximation algorithms can be implemented using a low complexity architecture, which can easily be pipelined to an arbitrary degree for increased throughput.

Place, publisher, year, edition, pages
Linköping University: Linköping University Electronic Press, 2008. p. 268
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1201
Keywords
FIR filters, Function approximation, Digital circuits, Computer arithmetic, Constant multiplication, Addition, Low power, Switching activity estimation
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-12576 (URN)978-91-7393-836-5 (ISBN)
Public defence
2008-10-03, Visionen, Hus B, Campus Valla, Linköping University, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2008-09-17 Created: 2008-09-15 Last updated: 2015-03-11Bibliographically approved
Tahmasbi Oskuii, S., Johansson, K., Gustafsson, O. & Kjeldsberg, P. G. (2008). Power optimization of weighted bit-product summation tree for elementary function generator. In: IEEE International Symposium on Circuits and Systems,2008 (pp. 1240). Piscataway, NJ: IEEE
Open this publication in new window or tab >>Power optimization of weighted bit-product summation tree for elementary function generator
2008 (English)In: IEEE International Symposium on Circuits and Systems,2008, Piscataway, NJ: IEEE , 2008, p. 1240-Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE, 2008
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-44134 (URN)10.1109/ISCAS.2008.4541649 (DOI)75779 (Local ID)75779 (Archive number)75779 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11
Johansson, K., Gustafsson, O. & Wanhammar, L. (2008). Switching activity estimation for shift-and-add based constant multipliers. In: IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008. (pp. 676-679). Piscataway, NJ: IEEE
Open this publication in new window or tab >>Switching activity estimation for shift-and-add based constant multipliers
2008 (English)In: IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., Piscataway, NJ: IEEE , 2008, , p. 676-679p. 676-679Conference paper, Published paper (Refereed)
Abstract [en]

In this work we propose a switching activity model for single adder multipliers. This correspond to the case where a signal is added to a shifted version of itself, which is a common part in multiple constant multiplication (MCM). Hence, the proposed model is suitable to be used in power consumption aware MCM algorithms. The model is shown to agree well with simulations, and for the studied test cases a maximum error of 0.26% is obtained.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE, 2008. p. 676-679
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-44135 (URN)10.1109/ISCAS.2008.4541508 (DOI)75780 (Local ID)75780 (Archive number)75780 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11
Wanhammar, L., Soltanian, B., Gustafsson, O. & Johansson, K. (2008). Synthesis of bandpass circulator-tree wave digital filters. In: 15th IEEE International Conference on Electronics, Circuits and Systems, 2008. ICECS 2008. (pp. 834-837). Piscataway, NJ: IEEE
Open this publication in new window or tab >>Synthesis of bandpass circulator-tree wave digital filters
2008 (English)In: 15th IEEE International Conference on Electronics, Circuits and Systems, 2008. ICECS 2008., Piscataway, NJ: IEEE , 2008, , p. 834-837p. 834-837Conference paper, Published paper (Refereed)
Abstract [en]

  In this paper, we discuss the design of bandpass circulator-tree wave digital filters derived from analog lowpass filters using the geometrical symmetric transformation. These structures are an interesting alternative to lattice WDFs showing a high modularity and posses the same properties as other WDF structures.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE, 2008. p. 834-837
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-44132 (URN)10.1109/ICECS.2008.4674983 (DOI)75762 (Local ID)75762 (Archive number)75762 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11
Johansson, K., Gustafsson, O. & Wanhammar, L. (2007). Bit-Level Optimization of Shift-and-Add Based FIR Filters. In: IEEE International Conference on Electronics, Circuits and Systems,2007 (pp. 713-716). Piscataway, NJ: IEEE
Open this publication in new window or tab >>Bit-Level Optimization of Shift-and-Add Based FIR Filters
2007 (English)In: IEEE International Conference on Electronics, Circuits and Systems,2007, Piscataway, NJ: IEEE , 2007, , p. 713-716p. 713-716Conference paper, Published paper (Refereed)
Abstract [en]

Implementation of FIR filters using shift-and-add multipliers has been an active research area for the last decade. However, almost all algorithms so far has been focused on reducing the number of adders and subtractors, while little effort was put on the bit-level implementation. In this work we propose a method to optimize the number of full adders and half adders required to realize a given number of additions. We present results which show that both area and power consumption can be reduced using the proposed method.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE, 2007. p. 713-716
Keywords
low power, low complexity, FIR filters, adder depth, multiple-constant multiplication
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-40719 (URN)53985 (Local ID)53985 (Archive number)53985 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11
Gustafsson, O., Tahmasbi Oskuii, S., Johansson, K. & Kjeldsberg, P. G. (2007). Switching activity reduction of MAC-based FIR filters with correlated input data. In: International Workshop on Power and Timing Modeling, Optimization and Simulation,2007 (pp. 526). Heidelberg: Springer
Open this publication in new window or tab >>Switching activity reduction of MAC-based FIR filters with correlated input data
2007 (English)In: International Workshop on Power and Timing Modeling, Optimization and Simulation,2007, Heidelberg: Springer , 2007, p. 526-Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Heidelberg: Springer, 2007
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-40577 (URN)53517 (Local ID)53517 (Archive number)53517 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11
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