liu.seSearch for publications in DiVA
Change search
Link to record
Permanent link

Direct link
BETA
Alvandpour, Atila
Alternative names
Publications (10 of 204) Show all publications
Hultman, M., Fredriksson, I., Larsson, M., Alvandpour, A. & Strömberg, T. (2018). A 15.6 frames per second 1 megapixel Multiple Exposure Laser Speckle Contrast Imaging setup. Journal of Biophotonics, 11(2), Article ID e201700069.
Open this publication in new window or tab >>A 15.6 frames per second 1 megapixel Multiple Exposure Laser Speckle Contrast Imaging setup
Show others...
2018 (English)In: Journal of Biophotonics, ISSN 1864-063X, E-ISSN 1864-0648, Vol. 11, no 2, article id e201700069Article in journal (Refereed) Published
Abstract [en]

A multiple exposure laser speckle contrast imaging (MELSCI) setup for visualizing blood perfusion was developed using a field programmable gate array (FPGA), connected to a 1000 frames per second (fps) 1-megapixel camera sensor. Multiple exposure time images at 1, 2, 4, 8, 16, 32 and 64 milliseconds were calculated by cumulative summation of 64 consecutive snapshot images. The local contrast was calculated for all exposure times using regions of 4 × 4 pixels. Averaging of multiple contrast images from the 64-millisecond acquisition was done to improve the signal-to-noise ratio. The results show that with an effective implementation of the algorithm on an FPGA, contrast images at all exposure times can be calculated in only 28 milliseconds. The algorithm was applied to data recorded during a 5 minutes finger occlusion. Expected contrast changes were found during occlusion and the following hyperemia in the occluded finger, while unprovoked fingers showed constant contrast during the experiment. The developed setup is capable of massive data processing on an FPGA that enables processing of MELSCI data in 15.6 fps (1000/64 milliseconds). It also leads to improved frame rates, enhanced image quality and enables the calculation of improved microcirculatory perfusion estimates compared to single exposure time systems.

Place, publisher, year, edition, pages
Wiley-VCH Verlagsgesellschaft, 2018
Keywords
blood flow, blood perfusion, FPGA, LASCA, LSCI, microcirculation, multiexposure
National Category
Other Medical Engineering
Identifiers
urn:nbn:se:liu:diva-141201 (URN)10.1002/jbio.201700069 (DOI)000424643600014 ()2-s2.0-85026753968 (Scopus ID)
Funder
Swedish Research Council, 2014-6141
Available from: 2017-09-26 Created: 2017-09-26 Last updated: 2018-03-07Bibliographically approved
Duong, Q.-T., Bhide, A. & Alvandpour, A. (2017). Design and analysis of high-speed split-segmented switched-capacitor DACs. Analog Integrated Circuits and Signal Processing, 92(2), 199-217
Open this publication in new window or tab >>Design and analysis of high-speed split-segmented switched-capacitor DACs
2017 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 92, no 2, p. 199-217Article in journal (Refereed) Published
Abstract [en]

In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area WCu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (WCu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.

Place, publisher, year, edition, pages
Springer-Verlag New York, 2017
Keywords
High-speed DACs, SC DACs, 12-bit split-segmented DACs, Linear output driver, Wideband wireless communications
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-137058 (URN)10.1007/s10470-017-0981-8 (DOI)000404899600003 ()
Note

Funding agencies: Swedish Foundation for Strategic Research

Available from: 2017-05-03 Created: 2017-05-03 Last updated: 2017-08-08Bibliographically approved
Harikumar, P., Wikner, J. & Alvandpour, A. (2016). A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications. IEEE Transactions on Circuits and Systems - II - Express Briefs, 63(8), 743-747
Open this publication in new window or tab >>A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications
2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, p. 743-747Article in journal (Refereed) Published
Abstract [en]

This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016
Keywords
Analog-to-digital converter, ADC, successive approximation register, SAR, ultra-low-voltage
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122729 (URN)10.1109/TCSII.2016.2531099 (DOI)000381440000007 ()978-1-4799-9877-7 (ISBN)
Note

At the time for thesis presentation publication was in status: Manuscript

Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2017-12-01Bibliographically approved
Zhang, D. & Alvandpour, A. (2016). A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS. IEEE Transactions on Circuits and Systems - II - Express Briefs, 63(3), 244-248
Open this publication in new window or tab >>A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS
2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 3, p. 244-248Article in journal (Refereed) Published
Abstract [en]

This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2016
Keywords
Digital error correction; nonbinary-weighted; redundancy; successive approximation register (SAR) analog-to-digital converter (ADC); successive approximation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-127444 (URN)10.1109/TCSII.2015.2482618 (DOI)000373136200004 ()
Available from: 2016-04-30 Created: 2016-04-26 Last updated: 2017-11-30
Chen, K., Harikumar, P. & Alvandpour, A. (2016). Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS. Analog Integrated Circuits and Signal Processing, 86(1), 87-98
Open this publication in new window or tab >>Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS
2016 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, p. 87-98Article in journal (Refereed) Published
Abstract [en]

This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

Place, publisher, year, edition, pages
Springer, 2016
Keywords
Pipelined SAR ADC; High resolution; OTA; Capacitive DAC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-124472 (URN)10.1007/s10470-015-0648-2 (DOI)000367750900011 ()
Available from: 2016-02-02 Created: 2016-02-01 Last updated: 2017-11-30Bibliographically approved
Bhide, A. & Alvandpour, A. (2015). A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 50(10), 2306-2310
Open this publication in new window or tab >>A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS
2015 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, p. 2306-2310Article in journal (Refereed) Published
Abstract [en]

This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

Place, publisher, year, edition, pages
IEEE, 2015
Keywords
ΔΣ DAC; 60 GHz radio; High speed; IEEE 80211ad; MASH; WiGig; time-interleaving
National Category
Signal Processing Computer Sciences
Identifiers
urn:nbn:se:liu:diva-120624 (URN)10.1109/JSSC.2015.2460375 (DOI)000362359700008 ()
Note

Funding text: Swedish Foundation for Strategic Research (SSF); Swedish Research Council (VR); Swedish Innovation Agency (VINNOVA)

Available from: 2015-08-19 Created: 2015-08-19 Last updated: 2018-01-11Bibliographically approved
Harikumar, P., Wikner, J. & Alvandpour, A. (2015). A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications. In: 2015 European Conference on Circuit Theory and Design (ECCTD): . Paper presented at 2015 European Conference on Circuit Theory and Design (ECCTD), August 24-26, Trondheim, Norway (pp. 13-16). IEEE
Open this publication in new window or tab >>A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications
2015 (English)In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 13-16Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68ï¿œ while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20oC +85oC].

Place, publisher, year, edition, pages
IEEE, 2015
Keywords
CMOS integrated circuits;analogue-digital conversion;mixed analogue-digital integrated circuits;operational amplifiers;silicon-on-insulator;PGA;SAR ADC;Si;UTBB FDSOI CMOS process;analog-mixed-signal circuits;continuous-time CMFB circuits;frequency 4.3 MHz;fully-differential OTA;gain 6 dB;gain 70 dB;operational transconductance amplifier;power 2.9 muW;programmable gain amplifier;reverse body bias;size 28 nm;temperature -20 degC to 85 degC;time 5.8 mus;ultrathin box and body fully-depleted silicon-on-insulator;voltage 1 V;word length 9 bit;Electronics packaging;Gain;Linearity;MOS devices;Resistors;Threshold voltage;Transistors
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122727 (URN)10.1109/ECCTD.2015.7300114 (DOI)000380498200096 ()978-1-4799-9877-7 (ISBN)
Conference
2015 European Conference on Circuit Theory and Design (ECCTD), August 24-26, Trondheim, Norway
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-09-25Bibliographically approved
Harikumar, P., Wikner, J. & Alvandpour, A. (2015). An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias. In: Proc. IEEE Nordic Circuits and Systems Conf. (NORCAS), Oslo, Norway, pp. 1-4, Oct. 2015: . Paper presented at 2015 NORCAS conference, IEEE Nordic Circuits and Systems Conference, 26-28 October, Oslo, Norway (pp. 1-4). IEEE
Open this publication in new window or tab >>An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias
2015 (English)In: Proc. IEEE Nordic Circuits and Systems Conf. (NORCAS), Oslo, Norway, pp. 1-4, Oct. 2015, IEEE , 2015, p. 1-4Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuoustime common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68o. Sufficient performance is maintained over process, supply voltage and temperature variations.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122728 (URN)10.1109/NORCHIP.2015.7364416 (DOI)000380441400063 ()978-1-4673-6576-5 (ISBN)
Conference
2015 NORCAS conference, IEEE Nordic Circuits and Systems Conference, 26-28 October, Oslo, Norway
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-09-16Bibliographically approved
Nielsen Lönn, M., Harikumar, P., Wikner, J. & Alvandpour, A. (2015). Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems. In: 2015 European Conference on Circuit Theory and Design (ECCTD): . Paper presented at European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, 24-26 Aug. 2015 (pp. 308-311). IEEE
Open this publication in new window or tab >>Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems
2015 (English)In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 308-311Conference paper, Published paper (Refereed)
Abstract [en]

MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

Place, publisher, year, edition, pages
IEEE, 2015
Keywords
energy harvesting, rectifier, low-voltage, piezo mems
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-123622 (URN)10.1109/ECCTD.2015.7300010 (DOI)000380498200012 ()9781479998760 (ISBN)9781479998777 (ISBN)
Conference
European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, 24-26 Aug. 2015
Available from: 2015-12-30 Created: 2015-12-30 Last updated: 2016-09-25Bibliographically approved
Bhide, A., Ojani, A. & Alvandpour, A. (2015). Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs. IEEE Transactions on Circuits and Systems - II - Express Briefs, 62(7), 646-650
Open this publication in new window or tab >>Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs
2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 7, p. 646-650Article in journal (Refereed) Published
Abstract [en]

Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
Keywords
Delta-sigma (Delta Sigma) modulator; digital Delta Sigma modulator; digital-to-analog converter (DAC); duty cycle; finite-impulse-response (FIR) filter; time interleaving
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-120215 (URN)10.1109/TCSII.2015.2415691 (DOI)000357126000006 ()
Note

Funding Agencies|Swedish Foundation for Strategic Research

Available from: 2015-07-21 Created: 2015-07-20 Last updated: 2017-12-04
Organisations

Search in DiVA

Show all publications