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Gannedahl, R., Asli, J. B., Sjöland, H. & Alvandpour, A. (2023). A Modular System-level Testbench for 6G Beamforming Applications with Near Circuit-Level Fidelity. In: NEWCAS 2023 CONFERENCE PROCEEDINGS: . Paper presented at 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, 26 - 28 June, 2023. IEEE
Open this publication in new window or tab >>A Modular System-level Testbench for 6G Beamforming Applications with Near Circuit-Level Fidelity
2023 (English)In: NEWCAS 2023 CONFERENCE PROCEEDINGS, IEEE, 2023Conference paper, Published paper (Refereed)
Abstract [en]

Sub-THz frequencies are tomorrow’s hot research area in mobile communication. However, in this range of frequencies the systems are complex, and it is hard to explore various system architectures and correlate the system-level solutions with circuit-level performances and requirements. This paper presents a scalable testbench in MATLAB/Simulink for sub-THz hybrid beamforming receivers. The testbench models analog and mixed signal blocks with high fidelity, enabling system level simulations with circuit-level imperfections. A receiver with multiple 4-element subarrays is simulated in the testbench, and the impact of phase noise, beam squint, phase shifter inaccuracies, ADC resolution, and more are investigated. Additionally, a Mueller-Müller symbol synchronizer is implemented to achieve symbol-rate sampling. 

Place, publisher, year, edition, pages
IEEE, 2023
Series
IEEE International New Circuits and Systems Conference, ISSN 2472-467X, E-ISSN 2474-9672
Keywords
Analog to digital conversion; MATLAB; Timing circuits; 6g; Circuit levels; Mobile communications; Modular system; Research areas; Sub-THz; System levels; System-level testbench.; Test-bench; THz frequencies; Beamforming
National Category
Telecommunications
Identifiers
urn:nbn:se:liu:diva-197694 (URN)10.1109/NEWCAS57931.2023.10198117 (DOI)001050763800087 ()2-s2.0-85168554493 (Scopus ID)9798350300246 (ISBN)9798350300253 (ISBN)
Conference
21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, 26 - 28 June, 2023
Note

Cited by: 0; Conference name: 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023; Conference date: 26 June 2023 through 28 June 2023; Conference code: 191480

Funding: Excellence Center at Linkoping-Lund in Information Technology (ELLIIT)

Available from: 2023-09-07 Created: 2023-09-07 Last updated: 2024-01-10
Asli, J. B., Saberkari, A. & Alvandpour, A. (2023). A Parallel-Path Amplifier for Fast Output Settling. In: NEWCAS 2023 CONFERENCE PROCEEDINGS: . Paper presented at 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, 26 - 28 June, 2023. IEEE
Open this publication in new window or tab >>A Parallel-Path Amplifier for Fast Output Settling
2023 (English)In: NEWCAS 2023 CONFERENCE PROCEEDINGS, IEEE, 2023Conference paper, Published paper (Refereed)
Abstract [en]

Pushing CMOS technology to the nanometer range is detrimental to analog circuits’ performance due to the reduction of gain and slew rate of amplifiers, so the classical approaches need to be revisited for adjustment in advanced nodes. This paper presents a parallel-path amplifier used as a switched-capacitor (SC) amplifier. The proposed amplifier includes a high bandwidth and slewing path parallel to a high gain path. The high bandwidth and slewing path, named the feedforward path, provides high charging/discharging currents to decrease the slewing time of the amplification phase, significantly (60%). In parallel, the high gain path provides sufficient open-loop DC gain for final settling (59 dB). The feedforward path is enabled/disabled by control signals provided through a hysteresis detector and by considering the status of the feedback voltage. The proposed amplifier is designed and fabricated in 65nm CMOS technology as a multiplying digital-to-analog converter (MDAC) in a pipeline ADC. The chip is under fabrication, and this paper covers post-layout performance of the proposed amplifier. The results reveal that enabling the feedforward path guarantees the amplifier to have a constant error (\lt2 mV) for an extensive range of input voltages (300 mV Vin 900 mV) compared to its standalone high gain path. At the same time, the static current of the feedforward path is minimal (\lt 100 µ A), and it can drive large load capacitors. © 2023 IEEE.

Place, publisher, year, edition, pages
IEEE, 2023
Series
IEEE International New Circuits and Systems Conference, ISSN 2472-467X, E-ISSN 2474-9672
Keywords
Bandwidth; CMOS integrated circuits; Feedback; CMOS technology; Digital-to-analog converters; Feedforward paths; High bandwidth; High gain; High-slewing path; Multiplying digital-to-analog converter; Nano meter range; Parallel path; Switched-capacitor amplifiers; Digital to analog conversion
National Category
Telecommunications
Identifiers
urn:nbn:se:liu:diva-197695 (URN)10.1109/NEWCAS57931.2023.10198175 (DOI)001050763800142 ()2-s2.0-85168548645 (Scopus ID)9798350300246 (ISBN)9798350300253 (ISBN)
Conference
21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, 26 - 28 June, 2023
Note

Funding: Excellence Center at Linkoping-Lund in Information Technology (ELLIIT)

Available from: 2023-09-07 Created: 2023-09-07 Last updated: 2024-01-10
Morales Chacon, O. A., Wikner, J., Svensson, C., Siek, L. & Alvandpour, A. (2022). Analysis of energy consumption bounds in CMOS current-steering digital-to-analog cosnverters. Analog Integrated Circuits and Signal Processing, 111, 339-351
Open this publication in new window or tab >>Analysis of energy consumption bounds in CMOS current-steering digital-to-analog cosnverters
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2022 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 111, p. 339-351Article in journal (Refereed) Published
Abstract [en]

In this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 2(2ENOB), whereas the speed-bound increases by 2(ENOB-2) and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2(ENOB-1). The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, f(s)/2.

Place, publisher, year, edition, pages
Springer, 2022
Keywords
Digital-to-analog converter; CMOS; Current-steering; High-speed; Energy; Power consumption bounds
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-184533 (URN)10.1007/s10470-022-02013-2 (DOI)000778220000001 ()
Note

Funding Agencies|Linko ping University

Available from: 2022-04-29 Created: 2022-04-29 Last updated: 2023-03-14Bibliographically approved
Morales Chacon, O., Wikner, J., Alvandpour, A. & Siek, L. (2022). Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters. In: 2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES): . Paper presented at 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), Wroclaw, POLAND, jun 23-24, 2022 (pp. 93-98). IEEE
Open this publication in new window or tab >>Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters
2022 (English)In: 2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), IEEE, 2022, p. 93-98Conference paper, Published paper (Refereed)
Abstract [en]

In this paper a comparative analysis of single- and dual-phase-clocked latch-driver circuits aimed at current-steering (CS) digital-to-analog converters (DACs) is presented. The design metrics of power consumption, propagation and switching delay as well as their product are considered. Moreover, an alternative latch-driver is proposed to sustain low-power consumption with short switching-delay. A 65 nm CMOS process is used and the results are obtained from post-layout simulations. In the analysis, dual-phase-clocked circuits consume about 2.4 x more power consumption and report 5.9 x shorter switching-delay with respect to the single-phase-clocked circuits. The proposed latch-driver consumes about 1.6 x more power with maintained switching-delay as the dual-phase-clocked solutions that leads to a reduction in the power-delay product of 25% and the lowest power-switching-delay product in the supply range 0.8-1.2 V.

Place, publisher, year, edition, pages
IEEE, 2022
Keywords
Current-steering DAC, high-speed, power consumption, latch-driver circuits, CMOS
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-188677 (URN)10.23919/MIXDES55591.2022.9837990 (DOI)000853346000016 ()9788363578220 (ISBN)
Conference
29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), Wroclaw, POLAND, jun 23-24, 2022
Note

Funding: Swedish innovation agency (VINNOVA) [2017-04891]; Swedish government (ELLIIT); Swedish foundation for international cooperation in research and higher education (STINT)

Available from: 2022-09-20 Created: 2022-09-20 Last updated: 2022-11-18
Morales Chacón, O., Wikner, J., Alvandpour, A. & Siek, L. (2021). A digital switching scheme to reduce DAC glitches using code-dependent randomization. In: 2021 IEEE Nordic Circuits and Systems Conference (NorCAS): . Paper presented at 2021 IEEE Nordic Circuits and Systems Conference (NorCAS), Oslo, Norway, 26-27 October 2021 (pp. 1-5). IEEE
Open this publication in new window or tab >>A digital switching scheme to reduce DAC glitches using code-dependent randomization
2021 (English)In: 2021 IEEE Nordic Circuits and Systems Conference (NorCAS), IEEE, 2021, p. 1-5Conference paper, Published paper (Refereed)
Abstract [en]

A digital switching scheme to reduce glitches and induce code-dependent randomization in digital-to-analog converters (DACs) is presented. The switching scheme is capable of generating a thermometer-like decoded bit sequence from a butterfly network. Due to the reduced switching activity, it mitigates the impact of timing issues, making it suitable for highspeed operation. From behavioral model simulations with a 10-bit current-steering DAC, a linearity improvement in spurious-free dynamic range of about 4 dBc is obtained for 10% amplitude mismatch in the current sources, demonstrating the improvement in linearity without the use of pseudo-random control signals.

Place, publisher, year, edition, pages
IEEE, 2021
Keywords
Digital-to-Analog Converter, Randomization, Butterfly Network
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-188674 (URN)10.1109/NorCAS53631.2021.9599651 (DOI)978-1-6654-0712-0 (ISBN)
Conference
2021 IEEE Nordic Circuits and Systems Conference (NorCAS), Oslo, Norway, 26-27 October 2021
Available from: 2022-09-20 Created: 2022-09-20 Last updated: 2022-11-18Bibliographically approved
Sundstrom, T., Asli, J. B., Svensson, C. & Alvandpour, A. (2020). A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS. In: 2020 IEEE Nordic Circuits and Systems Conference, NORCAS 2020 - Proceedings: . Paper presented at IEEE Nordic Circuits and Systems Conference (NORCAS), ELECTR NETWORK, oct 27-28, 2020. IEEE
Open this publication in new window or tab >>A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS
2020 (English)In: 2020 IEEE Nordic Circuits and Systems Conference, NORCAS 2020 - Proceedings, IEEE , 2020Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a pipeline analog-to-digital converter achieving 7.7 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used with asymmetrical biasing of the pMOS and nMOS transistors and digitally controlled binary-weighted assisted capacitor chain for calibration in the gain stage. It results in an increased closed-loop linearity and a THD of-53.1 dB while allowing symmetrical layout, transconductances, and parasitic effects. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary-weighted capacitor chain at gate of transistors which makes the power consumption of gain stage correction be avoided in digital domain. With a core power dissipation of 47.5 mW and an FoM of 0.355 pJ/conv-step, high sample rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency. © 2020 IEEE.

Place, publisher, year, edition, pages
IEEE, 2020
Keywords
Analog to digital converter, binaryweighted capacitor chain, inverter-based amplifier, pipeline, radix correction, single-channel, Analog to digital conversion, Calibration, CMOS integrated circuits, Energy efficiency, Digital domain, Digitally controlled, NMOS transistors, Parasitic effect, Pipeline analog-to-digital converters, Power overhead, Single-stage inverters, Switched capacitor, Pipelines
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-179890 (URN)10.1109/NorCAS51424.2020.9264994 (DOI)000722249100004 ()2-s2.0-85099787032 (Scopus ID)9781728192260 (ISBN)9781728192277 (ISBN)
Conference
IEEE Nordic Circuits and Systems Conference (NORCAS), ELECTR NETWORK, oct 27-28, 2020
Available from: 2021-10-04 Created: 2021-10-04 Last updated: 2024-01-10
Morales Chacón, O., Wikner, J., Alvandpour, A. & Siek, L. (2020). A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS. In: 2020 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): . Paper presented at IEEE Nordic Circuits and Systems Conference (NORCAS), ELECTR NETWORK, oct 27-28, 2020. IEEE
Open this publication in new window or tab >>A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS
2020 (English)In: 2020 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE, 2020Conference paper, Published paper (Refereed)
Abstract [en]

Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-mn CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220 mW for 58.6-pJ energy consumption per sample.

Place, publisher, year, edition, pages
IEEE, 2020
Keywords
5G; Current-Steering; Digital-to-Analog Converter; High Speed; CMOS; Radio Frequency; Low power
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-181638 (URN)10.1109/NorCAS51424.2020.9265003 (DOI)000722249100013 ()9781728192260 (ISBN)
Conference
IEEE Nordic Circuits and Systems Conference (NORCAS), ELECTR NETWORK, oct 27-28, 2020
Note

Funding Agencies|Swedens innovation agency (VINNOVA)Vinnova [2017-04891]; Swedish government (ELLIIT)

Available from: 2021-12-06 Created: 2021-12-06 Last updated: 2022-09-20
Qasemi, S. R., Rafati, M. & Alvandpour, A. (2020). A Low Power Front-end for Biomedical Fluorescence Sensing Applications. In: Jari Nurmi, Dag T. Wisland, Snorre Aunet, Kristian Kjelgaard (Ed.), 2020 IEEE Nordic Circuits and Systems Conference (NorCAS): . Paper presented at 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), Oslo, Norway, 27-28 Oct. 2020. IEEE
Open this publication in new window or tab >>A Low Power Front-end for Biomedical Fluorescence Sensing Applications
2020 (English)In: 2020 IEEE Nordic Circuits and Systems Conference (NorCAS) / [ed] Jari Nurmi, Dag T. Wisland, Snorre Aunet, Kristian Kjelgaard, IEEE, 2020Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a CMOS optical analog frontend for an implantable fluorescence biosensor for single-cell measurements. The front-end is configurable by a set of switches and consists of three integrated photodiodes (PD), three transimpedance amplifiers (TIA) for detecting a current range between 1 pA up to 10 mA. Also, ambient light and dark current canceling technique is proposed to make the sensor operate at different environmental conditions. The proposed front-end could be configured for ultra-low light detection or ultra-low power consumption. The circuit is simulated at the post-layout level. The minimum integrated input-referred current noise is obtained as 546 fA at the average power consumption of 1 μW for bandwidth (BW) of 1.4 kHz. For ultra-low-power configuration, the front-end has an average power consumption of 24 nW and input integrated current noise of 210 pA with 50 kHz BW.

Place, publisher, year, edition, pages
IEEE, 2020
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-179809 (URN)10.1109/NorCAS51424.2020.9264996 (DOI)000722249100006 ()9781728192260 (ISBN)9781728192277 (ISBN)
Conference
2020 IEEE Nordic Circuits and Systems Conference (NorCAS), Oslo, Norway, 27-28 Oct. 2020
Note

Funding: Swedish Foundation for Strategic Research (SSF)Swedish Foundation for Strategic Research [RMX18-0066]

Available from: 2021-10-04 Created: 2021-10-04 Last updated: 2021-12-06
Hultman, M., Fredriksson, I., Larsson, M., Alvandpour, A. & Strömberg, T. (2018). A 15.6 frames per second 1 megapixel Multiple Exposure Laser Speckle Contrast Imaging setup. Journal of Biophotonics, 11(2), Article ID e201700069.
Open this publication in new window or tab >>A 15.6 frames per second 1 megapixel Multiple Exposure Laser Speckle Contrast Imaging setup
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2018 (English)In: Journal of Biophotonics, ISSN 1864-063X, E-ISSN 1864-0648, Vol. 11, no 2, article id e201700069Article in journal (Refereed) Published
Abstract [en]

A multiple exposure laser speckle contrast imaging (MELSCI) setup for visualizing blood perfusion was developed using a field programmable gate array (FPGA), connected to a 1000 frames per second (fps) 1-megapixel camera sensor. Multiple exposure time images at 1, 2, 4, 8, 16, 32 and 64 milliseconds were calculated by cumulative summation of 64 consecutive snapshot images. The local contrast was calculated for all exposure times using regions of 4 × 4 pixels. Averaging of multiple contrast images from the 64-millisecond acquisition was done to improve the signal-to-noise ratio. The results show that with an effective implementation of the algorithm on an FPGA, contrast images at all exposure times can be calculated in only 28 milliseconds. The algorithm was applied to data recorded during a 5 minutes finger occlusion. Expected contrast changes were found during occlusion and the following hyperemia in the occluded finger, while unprovoked fingers showed constant contrast during the experiment. The developed setup is capable of massive data processing on an FPGA that enables processing of MELSCI data in 15.6 fps (1000/64 milliseconds). It also leads to improved frame rates, enhanced image quality and enables the calculation of improved microcirculatory perfusion estimates compared to single exposure time systems.

Place, publisher, year, edition, pages
Wiley-VCH Verlagsgesellschaft, 2018
Keywords
blood flow, blood perfusion, FPGA, LASCA, LSCI, microcirculation, multiexposure
National Category
Other Medical Engineering
Identifiers
urn:nbn:se:liu:diva-141201 (URN)10.1002/jbio.201700069 (DOI)000424643600014 ()2-s2.0-85026753968 (Scopus ID)
Funder
Swedish Research Council, 2014-6141
Available from: 2017-09-26 Created: 2017-09-26 Last updated: 2021-12-28Bibliographically approved
Duong, Q.-T., Bhide, A. & Alvandpour, A. (2017). Design and analysis of high-speed split-segmented switched-capacitor DACs. Analog Integrated Circuits and Signal Processing, 92(2), 199-217
Open this publication in new window or tab >>Design and analysis of high-speed split-segmented switched-capacitor DACs
2017 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 92, no 2, p. 199-217Article in journal (Refereed) Published
Abstract [en]

In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area WCu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (WCu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.

Place, publisher, year, edition, pages
Springer-Verlag New York, 2017
Keywords
High-speed DACs, SC DACs, 12-bit split-segmented DACs, Linear output driver, Wideband wireless communications
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-137058 (URN)10.1007/s10470-017-0981-8 (DOI)000404899600003 ()
Note

Funding agencies: Swedish Foundation for Strategic Research

Available from: 2017-05-03 Created: 2017-05-03 Last updated: 2019-09-05Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0001-8922-2360

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