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Svensson, Christer
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Publications (10 of 197) Show all publications
Morales Chacon, O. A., Wikner, J., Svensson, C., Siek, L. & Alvandpour, A. (2022). Analysis of energy consumption bounds in CMOS current-steering digital-to-analog cosnverters. Analog Integrated Circuits and Signal Processing, 111, 339-351
Open this publication in new window or tab >>Analysis of energy consumption bounds in CMOS current-steering digital-to-analog cosnverters
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2022 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 111, p. 339-351Article in journal (Refereed) Published
Abstract [en]

In this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 2(2ENOB), whereas the speed-bound increases by 2(ENOB-2) and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2(ENOB-1). The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, f(s)/2.

Place, publisher, year, edition, pages
Springer, 2022
Keywords
Digital-to-analog converter; CMOS; Current-steering; High-speed; Energy; Power consumption bounds
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-184533 (URN)10.1007/s10470-022-02013-2 (DOI)000778220000001 ()
Note

Funding Agencies|Linko ping University

Available from: 2022-04-29 Created: 2022-04-29 Last updated: 2023-03-14Bibliographically approved
Sundstrom, T., Asli, J. B., Svensson, C. & Alvandpour, A. (2020). A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS. In: 2020 IEEE Nordic Circuits and Systems Conference, NORCAS 2020 - Proceedings: . Paper presented at IEEE Nordic Circuits and Systems Conference (NORCAS), ELECTR NETWORK, oct 27-28, 2020. IEEE
Open this publication in new window or tab >>A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS
2020 (English)In: 2020 IEEE Nordic Circuits and Systems Conference, NORCAS 2020 - Proceedings, IEEE , 2020Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a pipeline analog-to-digital converter achieving 7.7 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used with asymmetrical biasing of the pMOS and nMOS transistors and digitally controlled binary-weighted assisted capacitor chain for calibration in the gain stage. It results in an increased closed-loop linearity and a THD of-53.1 dB while allowing symmetrical layout, transconductances, and parasitic effects. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary-weighted capacitor chain at gate of transistors which makes the power consumption of gain stage correction be avoided in digital domain. With a core power dissipation of 47.5 mW and an FoM of 0.355 pJ/conv-step, high sample rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency. © 2020 IEEE.

Place, publisher, year, edition, pages
IEEE, 2020
Keywords
Analog to digital converter, binaryweighted capacitor chain, inverter-based amplifier, pipeline, radix correction, single-channel, Analog to digital conversion, Calibration, CMOS integrated circuits, Energy efficiency, Digital domain, Digitally controlled, NMOS transistors, Parasitic effect, Pipeline analog-to-digital converters, Power overhead, Single-stage inverters, Switched capacitor, Pipelines
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-179890 (URN)10.1109/NorCAS51424.2020.9264994 (DOI)000722249100004 ()2-s2.0-85099787032 (Scopus ID)9781728192260 (ISBN)9781728192277 (ISBN)
Conference
IEEE Nordic Circuits and Systems Conference (NORCAS), ELECTR NETWORK, oct 27-28, 2020
Available from: 2021-10-04 Created: 2021-10-04 Last updated: 2024-01-10
Sundberg, C., Sjolin, M., Wikner, J., Svensson, C. & Danielsson, M. (2018). Increasing the dose efficiency in silicon photon-counting detectors utilizing dual shapers. In: PROCEEDINGS VOLUME 10573 SPIE MEDICAL IMAGING, 10-15 FEBRUARY 2018 Medical Imaging 2018: Physics of Medical Imaging: . Paper presented at SPIE Medical Imaging, 10-15 February, 2018, Houston, Texas, United States. SPIE - International Society for Optical Engineering, 10573, Article ID UNSP 105734W.
Open this publication in new window or tab >>Increasing the dose efficiency in silicon photon-counting detectors utilizing dual shapers
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2018 (English)In: PROCEEDINGS VOLUME 10573 SPIE MEDICAL IMAGING, 10-15 FEBRUARY 2018 Medical Imaging 2018: Physics of Medical Imaging, SPIE - International Society for Optical Engineering, 2018, Vol. 10573, article id UNSP 105734WConference paper, Published paper (Refereed)
Abstract [en]

Silicon photon-counting spectral detectors are candidates for the next generation of medical CT. For silicon detectors, a low noise floor is necessary to obtain good detection efficiency. A low noise floor can be obtained by having a slow shaping filter in the ASIC, but this leads to a long dead-time, thus decreasing the count-rate performance. In this work, we evaluate the benefit of utilizing two sub-channels with different shaping times. It is shown by simulation that utilizing a dual shaper can increase the dose efficiency for equal count-rate capability by up to 17%.

Place, publisher, year, edition, pages
SPIE - International Society for Optical Engineering, 2018
Series
Progress in Biomedical Optics and Imaging, ISSN 1605-7422 ; 10573
Keywords
dose efficiency; silicon detector; shaping time; ASIC; photon-counting
National Category
Atom and Molecular Physics and Optics
Identifiers
urn:nbn:se:liu:diva-151532 (URN)10.1117/12.2293453 (DOI)000436173700167 ()9781510616363 (ISBN)
Conference
SPIE Medical Imaging, 10-15 February, 2018, Houston, Texas, United States
Available from: 2018-09-24 Created: 2018-09-24 Last updated: 2019-04-23Bibliographically approved
Svensson, C., Persson, M., Sjölin, M. & Danielsson, M. (2018). X-ray detector system based on photon counting. us 15450653.
Open this publication in new window or tab >>X-ray detector system based on photon counting
2018 (English)Patent (Other (popular science, discussion, etc.))
Abstract [en]

Disclosed is an x-ray detector system including a multitude of detector elements, each connected to a respective photon counting channel for providing at least one photon count output, and a read-out unit connected to the photon counting channels for outputting the photon count outputs. Each one of at least a subset of the photon counting channels includes at least two photon counting sub-channels, each photon counting sub-channel providing at least one photon count output and having a shaping filter, wherein the shaping filters of the photon counting sub-channels are configured with different shaping times, and wherein the photon counting sub-channels, having shaping filters with different shaping times, are adapted for counting photons of different energy levels. Furthermore, the read-out unit is configured to select, for each photon counting channel, photon count outputs from the photon counting sub-channels.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-156491 (URN)
Patent
US 15450653 (2018-09-04)
Note

Grant Number: 10067240

Available from: 2019-04-24 Created: 2019-04-24 Last updated: 2019-04-24
Svensson, C. (2016). Letter: Response to the Comments by Willy Sansen on the paper "Towards Power Centric Analog Design," IEEE Circuits and Systems Magazine, vol. 15, no. 3, pp. 44-51, Sept. 2015. in IEEE CIRCUITS AND SYSTEMS MAGAZINE, vol 16, issue 1, pp 88-88 [Letter to the editor]. IEEE CIRCUITS AND SYSTEMS MAGAZINE, 16(1), 88-88
Open this publication in new window or tab >>Letter: Response to the Comments by Willy Sansen on the paper "Towards Power Centric Analog Design," IEEE Circuits and Systems Magazine, vol. 15, no. 3, pp. 44-51, Sept. 2015. in IEEE CIRCUITS AND SYSTEMS MAGAZINE, vol 16, issue 1, pp 88-88
2016 (English)In: IEEE CIRCUITS AND SYSTEMS MAGAZINE, ISSN 1531-636X, Vol. 16, no 1, p. 88-88Article in journal, Letter (Other academic) Published
Abstract [en]

n/a

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2016
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-126270 (URN)000370933600008 ()
Available from: 2016-03-21 Created: 2016-03-21 Last updated: 2016-04-11
He, Z., Chen, J., Svensson, C., Bao, L., Rhodin, A., Li, Y., . . . Zirath, H. (2015). A Hardware Efficient Implementation of a Digital Baseband Receiver for High-Capacity Millimeter-Wave Radios. IEEE transactions on microwave theory and techniques, 63(5), 1683-1692
Open this publication in new window or tab >>A Hardware Efficient Implementation of a Digital Baseband Receiver for High-Capacity Millimeter-Wave Radios
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2015 (English)In: IEEE transactions on microwave theory and techniques, ISSN 0018-9480, E-ISSN 1557-9670, Vol. 63, no 5, p. 1683-1692Article in journal (Refereed) Published
Abstract [en]

This paper presents an implementation solution for a digital baseband receiver, which consists mainly of an analog symbol timing recovery (STR) block and a digital carrier recovery block. The STR is realized based on "one-sample-per-symbol" sampling, resulting in relaxed requirement on the A/D converters sampling speed. In this sense, the proposed implementation solution is hardware efficient. To functionally verify the solution, a proof-of-concept E-band link system is implemented and tested in the laboratory, which supports 5-Gbit/s data traffic using 16 quadrature amplitude modulation. The test results demonstrate that the proposed solution works for high-capacity millimeter-wave radios for point-to-point links, one of the targeted applications.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
Keywords
Baseband receiver (Rx); E-band; point-to-point (PtP) radio; single sample per symbol; 16 quadrature amplitude modulation (16-QAM)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-118865 (URN)10.1109/TMTT.2015.2417541 (DOI)000354365900024 ()
Note

Funding Agencies|Swedish Foundation for Strategic Research (SSF); Vinnova

Available from: 2015-06-08 Created: 2015-06-04 Last updated: 2017-12-04
Svensson, C. (2015). Methods and QAM receiver for performing timing recovery. us 9,001,949.
Open this publication in new window or tab >>Methods and QAM receiver for performing timing recovery
2015 (English)Patent (Other (popular science, discussion, etc.))
Abstract [en]

A method in a QAM receiver (100) for performing timing recovery. The QAM receiver (100) is configured to receive a sequence of symbols. Each symbol is represented by a respective IQ pair comprising a respective inphase component I and a respective quadrature component Q. The QAM receiver (100) samples the respective I component and the respective Q component with a relative timing offset between the sampling of the respective I component and the respective Q component. The QAM receiver (100) establishes a first value associated to a quality of the I component samples, and a second value associated to a quality of the Q component samples, and compares the first value and second value to determine if the sampling timing should be advanced or delayed to improve the sample quality. The QAM receiver (100) adjusts subsequent sampling by advancing or delaying a sampling timing based on the comparison.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-122713 (URN)
Patent
US 9,001,949 (2015-04-07)
Available from: 2015-11-17 Created: 2015-11-17 Last updated: 2019-04-22Bibliographically approved
Svensson, C. (2015). Towards power centric analog design. IEEE Circuits and systems magazine, 15(3), 44-51
Open this publication in new window or tab >>Towards power centric analog design
2015 (English)In: IEEE Circuits and systems magazine, ISSN 1531-636X, Vol. 15, no 3, p. 44-51Article in journal (Refereed) Published
Abstract [en]

Power consumption of analog systems is poorly understoodtoday, in contrast to the very well developed analysis of digitalpower consumption. We show that there is good opportunity todevelop also the analog power understanding to a similar levelas the digital. Such an understanding will have a large impact inthe design of future electronic systems, where low power consumptionwill be crucial. Eventually we may reach a power centricanalog design methodology.

Place, publisher, year, edition, pages
IEEE Computer Society, 2015
Keywords
Electronics
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-120922 (URN)10.1109/MCAS.2015.2450671 (DOI)000361065600003 ()
Available from: 2015-08-31 Created: 2015-08-31 Last updated: 2019-12-02
Farahini, N., Hemani, A., Lansner, A., Clermidy, F. & Svensson, C. (2014). A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain. In: Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific: . Paper presented at The 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 20-23, 2014, Singapore (pp. 578-585). IEEE
Open this publication in new window or tab >>A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain
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2014 (English)In: Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, IEEE , 2014, p. 578-585Conference paper, Published paper (Refereed)
Abstract [en]

A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with 740 TFlops/s while accessing 30 TBs synaptic weights with a bandwidth of 112 TBs/s while consuming less than 6 kWs power for the typical case. This efficiency is three orders better than general purpose supercomputers in the same technology node.

Place, publisher, year, edition, pages
IEEE, 2014
Series
Asia and South Pacific Design Automation Conference Proceedings, ISSN 2153-6961
Keywords
DRAM chips;belief networks;biomedical electronics;brain;mainframes;medical computing;neural chips;neurophysiology;parallel machines;3D stacked DRAM memories;BCPNN model;Bayesian confidence propagation neural network model;custom designed logic chip;eBrain;general purpose supercomputers;human brain;hybrid memory cube;multichip custom digital supercomputer;scalable custom simulation machine;synaptic weights;technology node;Aggregates;Bandwidth;Brain modeling;Computational modeling;Delays;Random access memory;Three-dimensional displays
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-114646 (URN)10.1109/ASPDAC.2014.6742953 (DOI)000350791700104 ()2-s2.0-84897883326 (Scopus ID)978-1-4799-2816-3 (ISBN)
Conference
The 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 20-23, 2014, Singapore
Available from: 2015-03-02 Created: 2015-03-02 Last updated: 2015-04-23
Nilsson, E. & Svensson, C. (2014). Power Consumption of Integrated Low-Power Receivers. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 4(3), 273-283
Open this publication in new window or tab >>Power Consumption of Integrated Low-Power Receivers
2014 (English)In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, ISSN 2156-3357, E-ISSN 2156-3365, Vol. 4, no 3, p. 273-283Article in journal (Refereed) Published
Abstract [en]

With the advent of Internet of Things (IoT) it has become clear that radio-frequency (RF) designers have to be aware of power constraints, e.g., in the design of simplistic ultra-low power receivers often used as wake-up radios (WuRs). The objective of this work, one of the first systematic studies of power bounds for RF-systems, is to provide an overview and intuitive feel for how power consumption and sensitivity relates for low-power receivers. This was done by setting up basic circuit schematics for different radio receiver architectures to find analytical expressions for their output signal-to-noise ratio including power consumption, bandwidth, sensitivity, and carrier frequency. The analytical expressions and optimizations of the circuits give us relations between dc-energy-per-bit and receiver sensitivity, which can be compared to recent published low-power receivers. The parameter set used in the analysis is meant to reflect typical values for an integrated 90 nm complementary metal-oxide-semiconductor fabrication processes, and typical small sized RF lumped components.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2014
Keywords
Complementary metal-oxide-semiconductor (CMOS); Internet of things (IoT); low noise; low-power; receiver; wake-up radio (WuR)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-111454 (URN)10.1109/JETCAS.2014.2337151 (DOI)000342163700004 ()
Available from: 2014-10-21 Created: 2014-10-17 Last updated: 2024-01-05
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