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Pop, Paul
Publications (10 of 42) Show all publications
Pop, P., Goller, A., Pop, T. & Eles, P. (2012). Development Tools (1ed.). In: Roman Obermaisser (Ed.), Time-Triggered Communication: (pp. 361-493). Boca Raton, FL, USA: CRC Press
Open this publication in new window or tab >>Development Tools
2012 (English)In: Time-Triggered Communication / [ed] Roman Obermaisser, Boca Raton, FL, USA: CRC Press, 2012, 1, p. 361-493Chapter in book (Other academic)
Abstract [en]

Addressing key concepts, properties, and algorithms, this book offers a conceptual foundation of time-triggered communication. Contributions from experts help readers understand the various time-triggered communication protocols, including their differences and commonalities. Communication protocols covered include TTP, FlexRay, TTEthemet, SAFEbus, TTCAN and LIN. Protocols range from low-cost time-triggered fieldbus networks to ultra-reliable time-triggered networks for safety-critical applications. The text also presents information about the use of FlexRay in cars, TTP in railway and avionic systems, and TTEthemet in aerospace applications"-- 

  • "Embedded computers are by far the most common type of computer in use today. Ninety-eight percent of all computing devices are embedded in different kinds of electronic equipment such as automotive, industrial automation, telecommunications, consumer electronics and health/medical systems. Due to the many different and, partially, contradicting requirements, there exists no single model for building embedded systems. Well-known tradeoffs are predictability versus flexibility or resource adequacy versus best-effort strategies. Therefore, the chosen system model depends strongly on the requirements of the application"-- 
Place, publisher, year, edition, pages
Boca Raton, FL, USA: CRC Press, 2012 Edition: 1
Keywords
Networks on a chip -- Reliability, Fault tolerance (Engineering), Telecommunication systems -Reliability, Automatic timers
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-72201 (URN)978-1-4398-4661-2 (ISBN)
Available from: 2011-11-22 Created: 2011-11-22 Last updated: 2014-12-04Bibliographically approved
Izosimov, V., Polian, I., Pop, P., Eles, P. & Peng, Z. (2009). Analyse und Optimierung von fehlertoleranten Eingebetteten Systemen mit gehärteten Prozessoren. In: Zuverlässigkeit und Entwurf (ZUE), Stuttgart, Germany, September 21-23, 2009..
Open this publication in new window or tab >>Analyse und Optimierung von fehlertoleranten Eingebetteten Systemen mit gehärteten Prozessoren
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2009 (German)In: Zuverlässigkeit und Entwurf (ZUE), Stuttgart, Germany, September 21-23, 2009., 2009Conference paper, Published paper (Refereed)
Abstract [de]

Wir stellen einen Ansatz zur Entwurfsoptimierung von fehlertoleranten harten Echtzeitsystemen vor, der Hard-ware- und Software-Fehlertoleranztechniken kombiniert. Es wird zwischen selektiver Härtung in Hardware und Prozessneuausführungen in Software abgewogen, um benötigte Fehlertoleranz zu geringst möglichen Kosten zu erreichen. Die vorgestellten Entwurfsoptimierungsheuristiken legen die fehlertolerante Architektur und Prozess-zuordnung fest, so dass die Systemkosten minimiert, die Deadlines eingehalten und die Zuverlässigkeitsanforde-rungen erfüllt werden.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-59626 (URN)
Available from: 2010-09-29 Created: 2010-09-22 Last updated: 2010-09-29Bibliographically approved
Pop, P., Izosimov, V., Ion Eles, P. & Peng , Z. (2009). Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication. IEEE Transactions on VLSI Systems, 17(3), 389-402
Open this publication in new window or tab >>Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication
2009 (English)In: IEEE Transactions on VLSI Systems, ISSN 1063-8210 , Vol. 17, no 3, p. 389-402Article in journal (Refereed) Published
Abstract [en]

We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes and communications are statically scheduled. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that multiple transient faults are tolerated and the timing constraints of the application are satisfied. We present several design optimization approaches which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

Keywords
Fault tolerance, processor scheduling, real time systems, redundancy
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-17155 (URN)10.1109/TVLSI.2008.2003166 (DOI)
Available from: 2009-03-07 Created: 2009-03-07 Last updated: 2009-05-12
Pop, T., Pop, P., Eles, P. I., Peng, Z. & Andrei, A. (2008). Timing analysis of the FlexRay communication protocol. Real-time systems, 39(1-3), 205-235
Open this publication in new window or tab >>Timing analysis of the FlexRay communication protocol
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2008 (English)In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 39, no 1-3, p. 205-235Article in journal (Refereed) Published
Abstract [en]

FlexRay is a communication protocol heavily promoted on the market by a large group of car manufacturers and automotive electronics suppliers. However, before it can be successfully used for safety-critical applications that require predictability, timing analysis techniques are necessary for providing bounds for the message communication times. In this paper, we propose techniques for determining the timing properties of messages transmitted in both the static and the dynamic segments of a FlexRay communication cycle. The analysis techniques for messages are integrated in the context of a holistic schedulability analysis that computes the worst-case response times of all the tasks and messages in the system. We have evaluated the proposed analysis techniques using extensive experiments. We also present and evaluate three optimisation algorithms that can be used to improve the schedulability of a system that uses FlexRay. © 2007 Springer Science+Business Media, LLC.

Keywords
Distributed embedded systems, FlexRay, Real-time analysis
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-45678 (URN)10.1007/s11241-007-9040-3 (DOI)
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-13
Poulsen, K., Pop, P. & Izosimov, V. (2007). A Constraint Logic Programming Framework for the Synthesis of Fault-Tolerant Schedules for Distributed Embedded Systems. In: 12th IEEE Conf. on Emerging Technologies and Factory Automation Work-In-Progress Section,2007 (pp. 756). Patras, Greece: IEEE Computer Society Press
Open this publication in new window or tab >>A Constraint Logic Programming Framework for the Synthesis of Fault-Tolerant Schedules for Distributed Embedded Systems
2007 (English)In: 12th IEEE Conf. on Emerging Technologies and Factory Automation Work-In-Progress Section,2007, Patras, Greece: IEEE Computer Society Press , 2007, p. 756-Conference paper, Published paper (Refereed)
Abstract [en]

We present a constraint logic programming (CLP) approach for synthesis of fault-tolerant hard real-time applications on distributed heterogeneous architectures. We address time-triggered systems, where processes and messages are statically scheduled based on schedule tables. We use process re-execution for recovering from multiple transient faults. We propose three scheduling approaches, which each present a trade-off between schedule simplicity and performance, (i) full transparency, (ii) slack sharing and (iii) conditional, and provide various degrees of transparency. We have developed a CLP framework that produces the fault-tolerant schedules, guaranteeing schedulability in the presence of transient faults. We show how the framework can be used to tackle design optimization problems.The proposed approach has been evaluated using extensive experiments.

Place, publisher, year, edition, pages
Patras, Greece: IEEE Computer Society Press, 2007
Keywords
fault tolerance, embedded systems, design optimization, time-triggered systems, static scheduling, hard real-time
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-39306 (URN)47847 (Local ID)47847 (Archive number)47847 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-13
Pop, T., Pop, P., Eles, P. I. & Peng, Z. (2007). Bus Access Optimisation for FlexRay-based Distributed Embedded Systems. In: Design, Automation, and Test in Europe Conference DATE07,2007: . Paper presented at Design, Automation, and Test in Europe Conference DATE07 (pp. 51). Nice, France: IEEE Computer Society Press
Open this publication in new window or tab >>Bus Access Optimisation for FlexRay-based Distributed Embedded Systems
2007 (English)In: Design, Automation, and Test in Europe Conference DATE07,2007, Nice, France: IEEE Computer Society Press , 2007, p. 51-Conference paper, Published paper (Refereed)
Abstract [en]

FlexRay will very likely become the de-facto standard for in-vehicle communications. Its main advantage is the combination of high speed static and dynamic transmission of messages. In our previous work we have shown that not only the static but also the dynamic segment can be used for hard-real time communication in a deterministic manner. In this paper, we propose techniques for optimising the FlexRay bus access mechanism of a distributed system, so that the hard real-time deadlines are met for all the tasks and messages in the system. We have evaluated the proposed techniques using extensive experiments.

Place, publisher, year, edition, pages
Nice, France: IEEE Computer Society Press, 2007
Keywords
automotive electronics, FlexRay, bus access optimization, distributed systems
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-35882 (URN)10.1109/DATE.2007.364566 (DOI)28906 (Local ID)978-3-9810801-2-4 (ISBN)28906 (Archive number)28906 (OAI)
Conference
Design, Automation, and Test in Europe Conference DATE07
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-13
Poulsen, K., Pop, P. & Izosimov, V. (2007). Energy-Aware Synthesis of Fault-Tolerant Schedules for Real-Time Distributed Embedded Systems. In: 19th Euromicro Conference on Real-Time Systems ECRTS, Work-In-Progress Section,2007 (pp. 21). Pisa, Italy: IEEE Computer Society Press
Open this publication in new window or tab >>Energy-Aware Synthesis of Fault-Tolerant Schedules for Real-Time Distributed Embedded Systems
2007 (English)In: 19th Euromicro Conference on Real-Time Systems ECRTS, Work-In-Progress Section,2007, Pisa, Italy: IEEE Computer Society Press , 2007, p. 21-Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a design optimisation tool for distributed embedded real-time systems that 1) decides mapping, fault-tolerance policy and generates a fault-tolerant schedule, 2) is targeted for hard real-time, 3) has hard reliability goal, 4) generates static schedule for processes and messages, 5) provides fault-tolerance for k transient/soft faults, 6) optimises for minimal energy consumption, while considering impact of lowering voltages on the probability of faults, 7) uses constraint logic programming (CLP) based implementation.

Place, publisher, year, edition, pages
Pisa, Italy: IEEE Computer Society Press, 2007
Keywords
fault tolerance, embedded systems, design optimization, time-triggered systems, static scheduling, hard real-time, constraint logic programming
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-39307 (URN)47848 (Local ID)47848 (Archive number)47848 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-13
Pop, P., Poulsen, K., Izosimov, V. & Eles, P. I. (2007). Scheduling and Voltage Scaling for Energy/Reliability Trade-offs in Fault-Tolerant Time-Triggered Embedded Systems. In: 5th Intl. Conf. on Hardware/Software Codesign and System Synthesis CODES+ISSS,2007: . Paper presented at 5th Intl. Conf. on Hardware/Software Codesign and System Synthesis CODES+ISSS,2007 (pp. 233). Salzburg, Austria: IEEE Computer Society Press
Open this publication in new window or tab >>Scheduling and Voltage Scaling for Energy/Reliability Trade-offs in Fault-Tolerant Time-Triggered Embedded Systems
2007 (English)In: 5th Intl. Conf. on Hardware/Software Codesign and System Synthesis CODES+ISSS,2007, Salzburg, Austria: IEEE Computer Society Press , 2007, p. 233-Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present an approach to the scheduling and voltage scaling of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. Addressing simultaneously energy and reliability is especially challenging because lowering the voltage to reduce the energy consumption has been shown to exponentially increase the number of transient faults. In addition, time-redundancy based fault-tolerance techniques such as re-execution and dynamic voltage scaling-based low-power techniques are competing for the slack in the schedules. Our approach decides the voltage levels and start times of processes and the transmission times of messages, such that the transient faults are tolerated, the timing constraints of the application are satisfied and the energy is minimized. We present a constraint logic programming- based approach which is able to find reliable and schedulable implementations within limited energy and hardware resources. The developed algorithms have been evaluated using extensive experiments.

Place, publisher, year, edition, pages
Salzburg, Austria: IEEE Computer Society Press, 2007
Keywords
embedded systems, fault tolerance, low power, design optimization, reliability, transient faults
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-39305 (URN)10.1145/1289816.1289873 (DOI)47846 (Local ID)978-1-59593-824-4 (ISBN)47846 (Archive number)47846 (OAI)
Conference
5th Intl. Conf. on Hardware/Software Codesign and System Synthesis CODES+ISSS,2007
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-13
Pop, P., Eles, P. I. & Peng, Z. (2006). Analysis and optimisation of heterogeneous real-time embedded systems. In: Al-Hashimi, Bashir (Ed.), System On Chip: Next Generation Electronics (pp. 75-120). Stevenage, Herts, United Kingdom: The Institution of Engineering and Technology
Open this publication in new window or tab >>Analysis and optimisation of heterogeneous real-time embedded systems
2006 (English)In: System On Chip: Next Generation Electronics / [ed] Al-Hashimi, Bashir, Stevenage, Herts, United Kingdom: The Institution of Engineering and Technology , 2006, p. 75-120Chapter in book (Other academic)
Abstract [en]

We have presented an analysis for multi-cluster systems and outlined several characteristic design problems, related to the partitioning and mapping of functionality and the optimisation of the access to the communication infrastructure. An approach to schedulability-driven frame packing for the synthesis of multi-cluster systems was presented as an example of solving such a design optimisation problem. We have developed two optimisation heuristics for frame configuration synthesis which are able to determine frame configurations that lead to a schedulable system. We have shown that by considering the frame packing problem, we are able to synthesise schedulable hard real-time systems and to potentially reduce the overall cost of the architecture.

Place, publisher, year, edition, pages
Stevenage, Herts, United Kingdom: The Institution of Engineering and Technology, 2006
Series
IEE circuits, devices and systems series ; 18
Keywords
embedded systems, heterogeneous, real-time, analysis and optimization
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-31469 (URN)17259 (Local ID)0-86341-552-0 (ISBN)9780863415524 (ISBN)9781849190206 (ISBN)17259 (Archive number)17259 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2018-01-13Bibliographically approved
Pop, P., Eles, P. I., Peng, Z. & Pop, T. (2006). Analysis and optimization of distributed real-time embedded systems. ACM Transactions on Design Automation of Electronic Systems, 11(3), 593-625
Open this publication in new window or tab >>Analysis and optimization of distributed real-time embedded systems
2006 (English)In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 11, no 3, p. 593-625Article in journal (Refereed) Published
Abstract [en]

An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous not only in terms of hardware and software components, but also in terms of communication protocols and scheduling policies. In this context, the task of designing such systems is becoming increasingly difficult. The success of new adequate design methods depends on the availability of efficient analysis as well as optimization techniques. In this article, we present both analysis and optimization approaches for such heterogeneous distributed real-time embedded systems. More specifically, we discuss the schedulability analysis of hard real-time systems, highlighting particular aspects related to the heterogeneous and distributed nature of the applications. We also introduce several design optimization problems characteristic of this class of systems: mapping of functionality, the optimization of access to communication channel, and the assignment of scheduling policies to processes. Optimization heuristics aiming at producing a schedulable system with a given amount of resources are presented. © 2006 ACM.

Keywords
Algorithms, Design, Performance, Theory
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-50126 (URN)10.1145/1142980.1142984 (DOI)
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-12
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