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Izosimov, Viacheslav
Publications (10 of 20) Show all publications
Wang, Q., Wallin, A., Izosimov, V., Ingelsson, U. & Peng, Z. (2012). Test tool qualification through fault injection. In: Test Symposium (ETS 2012). Paper presented at 17th IEEE European Test Symposium (ETS 2012), Annecy, France, May 28-June 1, 2012. IEEE
Open this publication in new window or tab >>Test tool qualification through fault injection
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2012 (English)In: Test Symposium (ETS 2012), IEEE , 2012Conference paper, Poster (with or without abstract) (Other academic)
Abstract [en]

According to ISO 26262, a recent automotive functional safety standard, verification tools shall undergo qualification, e.g. to ensure that they do not fail to detect faults that can lead to violation of functional safety requirements. We present a semi-automatic qualification method involving a monitor and fault injection that reduce cost in the qualification process. We experiment on a verification tool implemented in LabVIEW.

Place, publisher, year, edition, pages
IEEE, 2012
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-91508 (URN)10.1109/ETS.2012.6233042 (DOI)978-1-4673-0696-6 (ISBN)e-978-1-4673-0695-9 (ISBN)
Conference
17th IEEE European Test Symposium (ETS 2012), Annecy, France, May 28-June 1, 2012
Available from: 2013-04-26 Created: 2013-04-26 Last updated: 2018-01-11
Izosimov, V., Di Guglielmo, G., Lora, M., Pravadelli, G., Fummi, F., Peng, Z. & Fujita, M. (2012). Time-Constraint-Aware Optimization of Assertions in Embedded Software. Journal of electronic testing, 28(4), 469-486
Open this publication in new window or tab >>Time-Constraint-Aware Optimization of Assertions in Embedded Software
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2012 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 28, no 4, p. 469-486Article in journal (Refereed) Published
Abstract [en]

Technology shrinking and sensitization have led to more and more transient faults in embedded systems. Transient faults are intermittent and non-predictable faults caused by external events, such as energetic particles striking the circuits. These faults do not cause permanent damages, but may affect the running applications. One way to ensure the correct execution of these embedded applications is to keep debugging and testing even after shipping of the systems, complemented with recovery/restart options. In this context, the executable assertions that have been widely used in the development process for design validation can be deployed again in the final product. In this way, the application will use the assertion to monitor itself under the actual execution and will not allow erroneous out-of-the-specification behavior to manifest themselves. This kind of software-level fault tolerance may represent a viable solution to the problem of developing commercial off-the-shelf embedded systems with dependability requirements. But software-level fault tolerance comes at a computational cost, which may affect time-constrained applications. Thus, the executable assertions shall be introduced at the best possible points in the application code, in order to satisfy timing constraints, and to maximize the error detection efficiency. We present an approach for optimization of executable assertion placement in time-constrained embedded applications for the detection of transient faults. In this work, assertions have different characteristics such as tightness, i.e., error coverage, and performance degradation. Taking into account these properties, we have developed an optimization methodology, which identifies candidate locations for assertions and selects a set of optimal assertions with the highest tightness at the lowest performance degradation. The set of selected assertions is guaranteed to respect the real-time deadlines of the embedded application. Experimental results have shown the effectiveness of the proposed approach, which provides the designer with a flexible infrastructure for the analysis of time-constrained embedded applications and transient-fault-oriented executable assertions.

Place, publisher, year, edition, pages
Springer Verlag (Germany), 2012
Keywords
Fault-detection optimization, Software-level fault tolerance, Time-constrained embedded software, Transient fault, Soft error, Executable assertion
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-84357 (URN)10.1007/s10836-012-5316-1 (DOI)000308364300007 ()
Available from: 2012-10-05 Created: 2012-10-05 Last updated: 2017-12-07
Lifa, A. A., Eles, P., Peng, Z. & Izosimov, V. (2010). Hardware/Software Optimization of Error Detection Implementation for Real-Time Embedded Systems. In: Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP International Conference on: . Paper presented at International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, USA, October 24-29, 2010. (pp. 41-50). IEEE Operations Center
Open this publication in new window or tab >>Hardware/Software Optimization of Error Detection Implementation for Real-Time Embedded Systems
2010 (English)In: Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP International Conference on, IEEE Operations Center , 2010, p. 41-50Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.

Place, publisher, year, edition, pages
IEEE Operations Center, 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-59634 (URN)10.1145/1878961.1878970 (DOI)978-1-60558-905-3 (ISBN)
Conference
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, USA, October 24-29, 2010.
Available from: 2010-09-29 Created: 2010-09-22 Last updated: 2014-09-18Bibliographically approved
Izosimov, V., Polian, I., Pop, P., Eles, P. & Peng, Z. (2009). Analyse und Optimierung von fehlertoleranten Eingebetteten Systemen mit gehärteten Prozessoren. In: Zuverlässigkeit und Entwurf (ZUE), Stuttgart, Germany, September 21-23, 2009..
Open this publication in new window or tab >>Analyse und Optimierung von fehlertoleranten Eingebetteten Systemen mit gehärteten Prozessoren
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2009 (German)In: Zuverlässigkeit und Entwurf (ZUE), Stuttgart, Germany, September 21-23, 2009., 2009Conference paper, Published paper (Refereed)
Abstract [de]

Wir stellen einen Ansatz zur Entwurfsoptimierung von fehlertoleranten harten Echtzeitsystemen vor, der Hard-ware- und Software-Fehlertoleranztechniken kombiniert. Es wird zwischen selektiver Härtung in Hardware und Prozessneuausführungen in Software abgewogen, um benötigte Fehlertoleranz zu geringst möglichen Kosten zu erreichen. Die vorgestellten Entwurfsoptimierungsheuristiken legen die fehlertolerante Architektur und Prozess-zuordnung fest, so dass die Systemkosten minimiert, die Deadlines eingehalten und die Zuverlässigkeitsanforde-rungen erfüllt werden.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-59626 (URN)
Available from: 2010-09-29 Created: 2010-09-22 Last updated: 2010-09-29Bibliographically approved
Izosimov, V., Polian, I., Pop, P., Ion Eles, P. & Peng, Z. (2009). Analysis and optimization of fault-tolerant embedded systems with hardened processors. In: Proceedings -Design, Automation and Test in Europe, DATE: . Paper presented at 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09; Nice; France (pp. 682-687).
Open this publication in new window or tab >>Analysis and optimization of fault-tolerant embedded systems with hardened processors
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2009 (English)In: Proceedings -Design, Automation and Test in Europe, DATE, 2009, p. 682-687Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process re-execution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of re-executions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-52965 (URN)10.1109/DATE.2009.5090752 (DOI)000273246700123 ()978-1-4244-3781-8 (ISBN)
Conference
2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09; Nice; France
Available from: 2010-01-14 Created: 2010-01-14 Last updated: 2014-09-04
Pop, P., Izosimov, V., Ion Eles, P. & Peng , Z. (2009). Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication. IEEE Transactions on VLSI Systems, 17(3), 389-402
Open this publication in new window or tab >>Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication
2009 (English)In: IEEE Transactions on VLSI Systems, ISSN 1063-8210 , Vol. 17, no 3, p. 389-402Article in journal (Refereed) Published
Abstract [en]

We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes and communications are statically scheduled. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that multiple transient faults are tolerated and the timing constraints of the application are satisfied. We present several design optimization approaches which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

Keywords
Fault tolerance, processor scheduling, real time systems, redundancy
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-17155 (URN)10.1109/TVLSI.2008.2003166 (DOI)
Available from: 2009-03-07 Created: 2009-03-07 Last updated: 2009-05-12
Izosimov, V. (2009). Scheduling and Optimization of Fault-Tolerant Distributed Embedded Systems. (Doctoral dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Scheduling and Optimization of Fault-Tolerant Distributed Embedded Systems
2009 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Safety-critical applications have to function correctly and deliver high level of quality-ofservice even in the presence of faults. This thesis deals with techniques for tolerating effects of transient and intermittent faults. Re-execution, software replication, and rollback recovery with checkpointing are used to provide the required level of fault tolerance at the software level. Hardening is used to increase the reliability of hardware components. These techniques are considered in the context of distributed real-time systems with static and quasi-static scheduling.

Many safety-critical applications have also strict time and cost constrains, which means that not only faults have to be tolerated but also the constraints should be satisfied. Hence, efficient system design approaches with careful consideration of fault tolerance are required. This thesis proposes several design optimization strategies and scheduling techniques that take fault tolerance into account. The design optimization tasks addressed include, among others, process mapping, fault tolerance policy assignment, checkpoint distribution, and trading-off between hardware hardening and software re-execution. Particular optimization approaches are also proposed to consider debugability requirements of fault-tolerant applications. Finally, quality-of-service aspects have been addressed in the thesis for fault-tolerant embedded systems with soft and hard timing constraints.

The proposed scheduling and design optimization strategies have been thoroughly evaluated with extensive experiments. The experimental results show that considering fault tolerance during system-level design optimization is essential when designing cost-effective and high-quality fault-tolerant embedded systems.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2009. p. 253
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1290
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-51727 (URN)978-91-7393-482-4 (ISBN)
Public defence
2009-12-16, Visionen, hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2009-11-16 Created: 2009-11-16 Last updated: 2009-11-25Bibliographically approved
Izosimov, V., Pop, P., Eles, P. I. & Peng, Z. (2008). Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints. In: Design, Automation, and Test in Europe DATE 2008,2008: . Paper presented at Design, Automation, and Test in Europe DATE 2008 (pp. 915). Munich, Germany: IEEE Computer Society Press
Open this publication in new window or tab >>Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints
2008 (English)In: Design, Automation, and Test in Europe DATE 2008,2008, Munich, Germany: IEEE Computer Society Press , 2008, p. 915-Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present an approach to the synthesis of fault-tolerant schedules for embedded applications with soft and hard real-time constraints. We are interested to guarantee the deadlines for the hard processes even in the case of faults, while maximizing the overall utility. We use time/utility functions to capture the utility of soft processes. A single static schedule computed off-line is not fault tolerant and is pessimistic in terms of utility, while a purely online approach, which computes a new schedule every time a process fails or completes, incurs an unacceptable overhead. Thus, we use a quasi-static scheduling strategy, where a set of schedules is synthesized off-line and, at run time, the scheduler will select the right schedule based on the occurrence of faults and the actual execution times of processes. The proposed schedule synthesis heuristics have been evaluated using extensive experiments.

Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press, 2008
Keywords
embedded systems, soft real-time, hard real-time, utility, design optimization, value-based, quasi-static scheduling
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-39636 (URN)10.1109/DATE.2008.4484791 (DOI)50428 (Local ID)978-3-9810801-3-1 (ISBN)978-3-9810801-4-8 (ISBN)50428 (Archive number)50428 (OAI)
Conference
Design, Automation, and Test in Europe DATE 2008
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-13
Eles, P. I., Izosimov, V., Pop, P. & Peng, Z. (2008). Synthesis of Fault-Tolerant Embedded Systems. In: Design, Automation and Test in Europe, 2008.. Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE 2008), 10-14 Mars 2008, Munich, Germany (pp. 960-965). Munich, Germany: IEEE
Open this publication in new window or tab >>Synthesis of Fault-Tolerant Embedded Systems
2008 (English)In: Design, Automation and Test in Europe, 2008., Munich, Germany: IEEE , 2008, p. 960-965Conference paper, Published paper (Refereed)
Abstract [en]

This work addresses the issue of design optimization for fault-tolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpointing with rollback recovery and active replication. Fault tolerant schedules are generated based on a conditional process graph representation. The formulated system synthesis approaches decide the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors, such that multiple transient faults are tolerated, transparency requirements are considered, and the timing constraints of the application are satisfied.

Place, publisher, year, edition, pages
Munich, Germany: IEEE, 2008
Series
Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
Keywords
embedded systems, fault tolerance, scheduling, mapping, policy assignment, transient faults
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-42253 (URN)10.1109/DATE.2008.4484825 (DOI)000257940700165 ()62056 (Local ID)978-3-9810801-3-1 (ISBN)e-978-3-9810801-4-8 (ISBN)62056 (Archive number)62056 (OAI)
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE 2008), 10-14 Mars 2008, Munich, Germany
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-12
Izosimov, V., Pop, P., Eles, P. I. & Peng, Z. (2008). Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems. In: 11th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN DSD 2008,2008: . Paper presented at 11th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN DSD 2008,2008 (pp. 71). Parma, Italy: IEEE Computer Society Press
Open this publication in new window or tab >>Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems
2008 (English)In: 11th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN DSD 2008,2008, Parma, Italy: IEEE Computer Society Press , 2008, p. 71-Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present an approach for scheduling with preemption for fault-tolerant embedded systems composed of soft and hard real-time processes. We are interested to maximize the overall utility for average, most likely to happen, scenarios and to guarantee the deadlines for the hard processes in the worst case scenarios. In many applications, the worst-case execution times of processes can be much longer than their average execution times. Thus, designs for the worst-case can be overly pessimistic, i.e., result in low overall utility. We propose preemption of process executions as a method to generate flexible schedules that maximize the overall utility for the average case while guarantee timing constraints in the worst case. Our scheduling algorithms determine off-line when to preempt and when to resurrect processes. The experimental results show the superiority of our new scheduling approach compared to approaches without preemption.

Place, publisher, year, edition, pages
Parma, Italy: IEEE Computer Society Press, 2008
Keywords
scheduling, fault tolerance, soft real-time, hard real-time, design optimization
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-42535 (URN)10.1109/DSD.2008.47 (DOI)65459 (Local ID)978-0-7695-3277-6 (ISBN)65459 (Archive number)65459 (OAI)
Conference
11th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN DSD 2008,2008
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-12
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