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Blad, Anton
Publications (10 of 22) Show all publications
Cipriano, A., Agostini, P., Blad, A. & Knopp, R. (2012). Cooperative Communications with HARQ in a Wireless Mesh Network Based on 3GPP LTE. In: Signal Processing Conference (EUSIPCO), 2012: . Paper presented at 20th European Signal Processing Conference (EUSIPCO 2012), 27-31 August 2012, Bucharest, Romania (pp. 1004-1008). IEEE
Open this publication in new window or tab >>Cooperative Communications with HARQ in a Wireless Mesh Network Based on 3GPP LTE
2012 (English)In: Signal Processing Conference (EUSIPCO), 2012, IEEE , 2012, p. 1004-1008Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents some results from of the FP7 ICT-LOLA (achieving LOw LAtency in wireless communications) project on the design of clusterized wireless mesh network based on 3GPP LTE. First, we focus on the general MAC/PHY structure of the clusterized mesh network based on 3GPP LTE. Then, the concept of virtual link is presented for inter-cluster communications combining MAC layer forwarding, hybrid automatic repeat request (HARQ) and cooperative communications with Decode and Forward (DF). The goal of a virtual link is to enable low latency data transfer in inter-cluster communications. The virtual link solution is studied by simulations thanks to OpenAirInterface which integrates LTE MAC and PHY layer procedures, as well as adaptations needed for the LOLA wireless mesh network. Simulation results show that the proposed distributed solution smoothly adapts to the link conditions. A loss in throughput efficiency is the price to be paid in certain configurations for the distributed operation of the virtual link. Nevertheless, the technique helps in reducing the average number of transmissions thus contributing to improve the latency of the system.

Place, publisher, year, edition, pages
IEEE, 2012
Series
European Signal Processing Conference, ISSN 2219-5491
Keywords
3GPP LTE; wireless mesh networks; MAC layer forwarding; hybrid automatic repeat request (HARQ); cooperative communications; decode and forward (DF); low latency
National Category
Communication Systems
Identifiers
urn:nbn:se:liu:diva-77993 (URN)978-1-4673-1068-0 (ISBN)
Conference
20th European Signal Processing Conference (EUSIPCO 2012), 27-31 August 2012, Bucharest, Romania
Projects
FP7 LOLA
Available from: 2012-06-04 Created: 2012-06-04 Last updated: 2014-06-05Bibliographically approved
Blad, A., Axell, E. & Larsson, E. G. (2012). Spectrum Sensing of OFDM Signals in the Presence of CFO: New Algorithms and Empirical Evaluation Using USRP. In: Proceedings of the 13th IEEE International Workshop on Signal Processing Advances in Wireless Communications (SPAWC): . Paper presented at The 13th IEEE International Workshop on Signal Processing Advances in Wireless Communications (SPAWC) (pp. 159-163). IEEE
Open this publication in new window or tab >>Spectrum Sensing of OFDM Signals in the Presence of CFO: New Algorithms and Empirical Evaluation Using USRP
2012 (English)In: Proceedings of the 13th IEEE International Workshop on Signal Processing Advances in Wireless Communications (SPAWC), IEEE , 2012, p. 159-163Conference paper, Published paper (Refereed)
Abstract [en]

In this work, we consider spectrum sensing of OFDM signals. We deal withthe inevitable problem of a carrier frequency offset, and propose modificationsto some state-of-the-art detectors to cope with that. Moreover, the (modified)detectors are implemented using GNU radio and USRP, and evaluated over aphysical radio channel. Measurements show that all of the evaluated detectorsperform quite well, and the preferred choice of detector depends on thedetection requirements and the radio environment.

Place, publisher, year, edition, pages
IEEE, 2012
Series
IEEE International Workshop on Signal Processing Advances in Wireless Communications, ISSN 1948-3244
National Category
Communication Systems Telecommunications
Identifiers
urn:nbn:se:liu:diva-76673 (URN)10.1109/SPAWC.2012.6292878 (DOI)000320276200033 ()978-1-4673-0969-1 (ISBN)978-1-4673-0970-7 (ISBN)978-1-4673-0971-4 (ISBN)
Conference
The 13th IEEE International Workshop on Signal Processing Advances in Wireless Communications (SPAWC)
Funder
eLLIIT - The Linköping‐Lund Initiative on IT and Mobile CommunicationsSwedish Research CouncilKnut and Alice Wallenberg Foundation
Available from: 2012-04-16 Created: 2012-04-16 Last updated: 2016-08-31
Blad, A. & Gustafsson, O. (2011). FPGA implementation of rate-compatible QC-LDPC code decoder. In: : . Paper presented at European Conference on Circuit Theory and Design, August 29-31, Linköping, Sweden (pp. 777-780).
Open this publication in new window or tab >>FPGA implementation of rate-compatible QC-LDPC code decoder
2011 (English)Conference paper, Published paper (Other academic)
Abstract [en]

The use of rate-compatible error correcting codes offers severaladvantages as compared to the use of fixed-rate codes: a smooth adaptationto the channel conditions, the possibility of incremental Hybrid ARQschemes, as well as simplified code representations in the encoder anddecoder. In this paper, the implementation of a decoder for rate-compatiblequasi-cyclic LDPC codes is considered. The decoder uses check node mergingto increase the convergence speed of the algorithm. Check node mergingallows the decoder to achieve the same performance with a significantlylower number of iterations, thereby increasing the throughput.

The feasibility of a check node merging decoder is investigated for codesfrom IEEE 802.16e and IEEE 802.11n. The faster convergence rate of the checknode merging algorithm allows the decoder to be implemented using lowerparallelization factors, thereby reducing the logic complexity. The designshave been synthesized to an Altera Cyclone II FPGA, and results showsignificant increases in throughput at high SNR.

National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-70821 (URN)10.1109/ECCTD.2011.6043844 (DOI)978-1-4577-0616-5 (ISBN)978-1-4577-0617-2 (ISBN)
Conference
European Conference on Circuit Theory and Design, August 29-31, Linköping, Sweden
Available from: 2011-09-20 Created: 2011-09-19 Last updated: 2015-03-11Bibliographically approved
Blad, A. (2011). Low Complexity Techniques for Low Density Parity Check Code Decoders and Parallel Sigma-Delta ADC Structures. (Doctoral dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Low Complexity Techniques for Low Density Parity Check Code Decoders and Parallel Sigma-Delta ADC Structures
2011 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, with uncomplicated arithmetic operations and low accuracy requirements, the random structure and irregularity of a theoretically well-defined code does not easily allow efficient VLSI implementations. Thus the LDPC decoding algorithm can be said to be communication-bound rather than computation-bound.

In this thesis, a modification to the sum-product decoding algorithm called earlydecision decoding is suggested. The modification is based on the idea that the values of the bits in a block can be decided individually during decoding. As the sumproduct decoding algorithm is a soft-decision decoder, a reliability can be defined for each bit. When the reliability of a bit is above a certain threshold, the bit can be removed from the rest of the decoding process, and thus the internal communication associated with the bit can be removed in subsequent iterations. However, with the early decision modification, an increased error probability is associated. Thus, bounds on the achievable performance as well as methods to detect graph inconsistencies resulting from erroneous decisions are presented. Also, a hybrid decoder achieving a negligible performance penalty compared to the sum-product decoder is presented. With the hybrid decoder, the internal communication is reduced with up to 40% for a rate-1/2 code with a length of 1152 bits, whereas increasing the rate allows significantly higher gains.

The algorithms have been implemented in a Xilinx Virtex 5 FPGA, and the resulting slice utilization and energy dissipation have been estimated. However, due to increased logic overhead of the early decision decoder, the slice utilization increases from 14.5% to 21.0%, whereas the logic energy dissipation reduction from 499 pJ to 291 pJ per iteration and bit is offset by the clock distribution power, increased from 141 pJ to 191 pJ per iteration and bit. Still, the early decision decoder shows a net 16% estimated decrease of energy dissipation.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2011. p. 180
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1385
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-69432 (URN)978-91-7393-104-5 (ISBN)
Public defence
2011-09-06, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2011-08-18 Created: 2011-06-28 Last updated: 2019-12-19Bibliographically approved
Blad, A., Gustafsson, O., Zheng, M. & Fei, Z. (2010). Integer linear programming based optimization of puncturing sequences for quasi-cyclic low-density parity-check codes. In: Proceedings of International Symposium on Turbo Codes and Iterative Information Processing. IEEE
Open this publication in new window or tab >>Integer linear programming based optimization of puncturing sequences for quasi-cyclic low-density parity-check codes
2010 (English)In: Proceedings of International Symposium on Turbo Codes and Iterative Information Processing, IEEE , 2010Conference paper, Published paper (Refereed)
Abstract [en]

An optimization algorithm for the design of puncturing patterns for low-density parity-check codes is proposed. The algorithm is applied to the base matrix of a quasi-cyclic code, and is expanded for each block size used. Thus, storing puncturing patterns specific to each block size is not required. Using the optimization algorithm, the number of 1-step recoverable nodes in the base matrix is maximized. The obtained sequence is then used as a base to obtain longer puncturing sequences by a sequential increase of the allowed recovery delay. The proposed algorithm is compared to one previous greedy algorithm, and shows superior performance for high rates when the heuristics are applied to the base matrix in order to create block size-independent puncturing patterns.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-65507 (URN)10.1109/ISTC.2010.5613847 (DOI)
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2015-03-11
Blad, A. & Gustafsson, O. (2010). Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 29(1), 81-101
Open this publication in new window or tab >>Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures
2010 (English)In: CIRCUITS SYSTEMS AND SIGNAL PROCESSING, ISSN 0278-081X, Vol. 29, no 1, p. 81-101Article in journal (Refereed) Published
Abstract [en]

Analog-to-digital converters based on sigma-delta modulation have shown promising performance, with steadily increasing bandwidth. However, associated with the increasing bandwidth is an increasing modulator sampling rate, which becomes costly to decimate in the digital domain. Several architectures exist for the digital decimation filter, and among the more common and efficient are polyphase decomposed finite-length impulse response (FIR) filter structures. In this paper, we consider such filters implemented with partial product generation for the multiplications, and carry-save adders to merge the partial products. The focus is on the efficient pipelined reduction of the partial products, which is done using a bit-level optimization algorithm for the tree design. However, the method is not limited only to filter design, but may also be used in other applications where high-speed reduction of partial products is required. The presentation of the reduction method is carried out through a comparison between the main architectural choices for FIR filters: the direct-form and transposed direct-form structures. For the direct-form structure, usage of symmetry adders for linear-phase filters is investigated, and a new scheme utilizing partial symmetry adders is introduced. The optimization results are complemented with energy dissipation and cell area estimations for a 90 nm CMOS process.

Keywords
FIR, Polyphase, Sigma-delta, CIC, Optimization, Integer linear programming, Decimation, Digital filter, Carry-save
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-53826 (URN)10.1007/s00034-009-9116-5 (DOI)000273808300006 ()
Note
The original publication is available at www.springerlink.com: Anton Blad and Oscar Gustafsson, Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures, 2010, CIRCUITS SYSTEMS AND SIGNAL PROCESSING, (29), 1, 81-101. http://dx.doi.org/10.1007/s00034-009-9116-5 Copyright: Springer Science Business Media http://www.springerlink.com/ Available from: 2010-02-05 Created: 2010-02-05 Last updated: 2015-03-11
Abbas, M., Gustafsson, O. & Blad, A. (2010). Low-Complexity Parallel Evaluation of Powers Exploiting Bit-Level Redundancy. In: Michael B. Matthews (Ed.), Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010. Paper presented at Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 , Pacific Grove, CA, USA (pp. 1168-1172). Washington, DC, USA: IEEE Computer Society
Open this publication in new window or tab >>Low-Complexity Parallel Evaluation of Powers Exploiting Bit-Level Redundancy
2010 (English)In: Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 / [ed] Michael B. Matthews, Washington, DC, USA: IEEE Computer Society , 2010, p. 1168-1172Conference paper, Published paper (Refereed)
Abstract [en]

In this work, we investigate the problem of computing any requested set of power terms in parallel using summations trees. This problem occurs in applications like polynomial approximation, Farrow filters (polynomial evaluation part) etc. In the proposed technique, the partial product of each power term is initially computed independently. A redundancy check is then made in each and among all partial products matrices at bit level. The redundancy here relates to the fact that same three partial products may be present in more than one columns, and, hence, can be mapped to the same full adder. The proposed algorithm is tested for different sets of powers and wordlengths to exploit the sharing potential.

Place, publisher, year, edition, pages
Washington, DC, USA: IEEE Computer Society, 2010
Series
Asilomar Conference on Signals, Systems and Computers. Conference Record, ISSN 1058-6393
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-70453 (URN)10.1109/ACSSC.2010.5757714 (DOI)978-1-4244-9722-5 (ISBN)
Conference
Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 , Pacific Grove, CA, USA
Available from: 2011-09-20 Created: 2011-09-08 Last updated: 2015-03-11Bibliographically approved
Zheng, M., Fei, Z., Chen, X., Kuang, J. & Blad, A. (2010). Power Efficient Partial Repeated Cooperation Scheme with Regular LDPC Code. In: Proceedings of Vehicular Technology Conference, Spring. IEEE
Open this publication in new window or tab >>Power Efficient Partial Repeated Cooperation Scheme with Regular LDPC Code
Show others...
2010 (English)In: Proceedings of Vehicular Technology Conference, Spring, IEEE , 2010Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
IEEE, 2010
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-65502 (URN)10.1109/VETECS.2010.5494080 (DOI)
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2011-02-11
Blad, A., Gustafsson, O., Zheng, M. & Fei, Z. (2010). Rate-compatible LDPC code decoder using check-node merging. In: Proceedings of Asilomar Conference on Signals, Systems and Computers: . Paper presented at 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010; Pacific Grove, CA; United States (pp. 1119-1123). IEEE
Open this publication in new window or tab >>Rate-compatible LDPC code decoder using check-node merging
2010 (English)In: Proceedings of Asilomar Conference on Signals, Systems and Computers, IEEE , 2010, p. 1119-1123Conference paper, Published paper (Refereed)
Abstract [en]

The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as sharing of the encoder and decoder implementations between the codes of different rates. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. Assuming the use of a code ensemble obtained through puncturing of a low-rate mother code, the decoder achieves significantly reduced convergence rates by merging the check node neighbours of the punctured variable nodes. The architecture uses the min-sum algorithm with serial node processing elements to efficiently handle the wide spread of node degrees that results from the merging of the check nodes.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-65508 (URN)10.1109/ACSSC.2010.5757578 (DOI)978-1-4244-9722-5 (ISBN)
Conference
44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010; Pacific Grove, CA; United States
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2015-03-11
Blad, A. & Gustafsson, O. (2010). Redundancy reduction for high-speed FIR filter architectures based on carry-save adder trees. In: International Symposium on Circuits and Systems. IEEE
Open this publication in new window or tab >>Redundancy reduction for high-speed FIR filter architectures based on carry-save adder trees
2010 (English)In: International Symposium on Circuits and Systems, IEEE , 2010Conference paper, Published paper (Refereed)
Abstract [en]

In this work we consider high-speed FIR filter architectures implemented using, possibly pipelined, carry-save adder trees for accumulating the partial products. In particular we focus on the mapping between partial products and full adders and propose a technique to reduce the number of carry-save adders based on the inherent redundancy of the partial products. The redundancy reduction is performed on the bit-level to also work for short wordlength data such as those obtained from sigma-delta modulators.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-65501 (URN)10.1109/ISCAS.2010.5537997 (DOI)
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2015-03-11
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