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Jervan, Gert
Publications (10 of 25) Show all publications
Jervan, G., Eles, P. I., Peng, Z., Ubar, R. & Jenihhin, M. (2006). Test time minimization for hybrid BIST of core-based systems. Journal of Computer Science and Technology, 21(6), 907-912
Open this publication in new window or tab >>Test time minimization for hybrid BIST of core-based systems
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2006 (English)In: Journal of Computer Science and Technology, ISSN 1000-9000, E-ISSN 1860-4749, Vol. 21, no 6, p. 907-912Article in journal (Refereed) Published
Abstract [en]

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions. © Springer Science + Business Media, Inc. 2006.

Keywords
Hybrid BIST, Self-test, SoC
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-50096 (URN)10.1007/s11390-006-0907-x (DOI)
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-12
Jervan, G., Ubar, R., Peng, Z. & Eles, P. I. (2005). An Approach to System-Level DFT. In: M. Sonza Reorda, Z. Peng, M. Violante (Ed.), System-level Test and Validation of Hardware/Software Systems: (pp. 121-149). Berlin: Springer Berlin Heidelberg
Open this publication in new window or tab >>An Approach to System-Level DFT
2005 (English)In: System-level Test and Validation of Hardware/Software Systems / [ed] M. Sonza Reorda, Z. Peng, M. Violante, Berlin: Springer Berlin Heidelberg , 2005, p. 121-149Chapter in book (Other academic)
Abstract [en]

New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.

As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue.

System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:

• modeling of bugs and defects;

• stimulus generation for validation and test purposes (including timing errors;

• design for testability.

For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.

Place, publisher, year, edition, pages
Berlin: Springer Berlin Heidelberg, 2005
Series
Springer Series in Advanced Microelectronics ; 17
Keywords
testing, design for testability
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-28489 (URN)13637 (Local ID)1-85233-899-7 (ISBN)978-1-84628-145-7 (ISBN)13637 (Archive number)13637 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2018-01-13Bibliographically approved
Jervan, G., Peng, Z., Ubar, R. & Korelina, O. (2005). An Improved Estimation Technique for Hybrid BIST Test Set Generation. In: IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems DDECS,2005 (pp. 182). Sopron, Hungary: IEEE Computer Society Press
Open this publication in new window or tab >>An Improved Estimation Technique for Hybrid BIST Test Set Generation
2005 (English)In: IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems DDECS,2005, Sopron, Hungary: IEEE Computer Society Press , 2005, p. 182-Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an improved estimation technique for hybrid BIST test set generation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is determined by the ratio of those test patterns in the final test set. Unfortunately, exact algorithms for finding the optimal test sets are computationally very expensive. And several heuristics have been developed to address this problem based on estimation methods. In this paper we propose an improved estimation technique for fast generation of the hybrid test set. The technique is based on fault simulation results, and experiments have shown that the proposed technique is more accurate than the estimation methods proposed earlier.

Place, publisher, year, edition, pages
Sopron, Hungary: IEEE Computer Society Press, 2005
Keywords
hybrid BIST, pseudorandom test pattern, deterministic test pattern, estimation technique
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-24569 (URN)6738 (Local ID)6738 (Archive number)6738 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
Jervan, G., Ubar, R., Shchenova, T. & Peng, Z. (2005). Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. In: 10th IEEE European Test Symposium ETS´05,2005: . Paper presented at 10th IEEE European Test Symposium ETS´05. Tallinn, Estonia: IEEE Computer Society Press
Open this publication in new window or tab >>Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment
2005 (English)In: 10th IEEE European Test Symposium ETS´05,2005, Tallinn, Estonia: IEEE Computer Society Press , 2005Conference paper, Published paper (Refereed)
Abstract [en]

This paper addresses the energy minimization problem for system-on-chip testing. We assume a hybrid BIST test architecture where a combination of deterministic and pseudorandom test sequences is used. The objective of our proposed technique is to find the best ratio of these sequences so that the total energy is minimized and the memory requirements for the deterministic test set are met without sacrificing test quality. We propose two different heuristic algorithms and a fast estimation method that enables considerable reduction of the computation time. Experimental results have shown the efficiency of the approach for finding reduced energy solutions with low computational overhead.

Place, publisher, year, edition, pages
Tallinn, Estonia: IEEE Computer Society Press, 2005
Keywords
system-on-chip, testing, hybrid BIST, energy minimization, deterministic test sequence, pseudorandom test sequence
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-24568 (URN)10.1109/ETS.2005.16 (DOI)6737 (Local ID)0-7695-2341-2 (ISBN)6737 (Archive number)6737 (OAI)
Conference
10th IEEE European Test Symposium ETS´05
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
Jervan, G. (2005). Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems. (Doctoral dissertation). : Institutionen för datavetenskap
Open this publication in new window or tab >>Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems
2005 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing methods, most of which are based on low-level representations of the hardware circuits. Therefore, more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. At the same time, the automatic test equipment based solutions have failed to deliver the required test quality. As a result, alternative testing methods have been studied, which has led to the development of built-in self-test (BIST) techniques.

In this thesis, we present a novel hybrid BIST technique that addresses several areas where classical BIST methods have shortcomings. The technique makes use of both pseudorandom and deterministic testing methods, and is devised in particular for testing modern systems-on-chip. One of the main contributions of this thesis is a set of optimization methods to reduce the hybrid test cost while not sacrificing test quality. We have devel oped several optimization algorithms for different hybrid BIST architectures and design constraints. In addition, we have developed hybrid BIST scheduling methods for an abort-on-first-fail strategy, and proposed a method for energy reduction for hybrid BIST.

Devising an efficient BIST approach requires different design modifications, such as insertion of scan paths as well as test pattern generators and signature analyzers. These modifications require careful testability analysis of the original design. In the latter part of this thesis, we propose a novel hierarchical test generation algorithm that can be used not only for manufacturing tests but also for testability analysis. We have also investigated the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation.

Experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodologies and techniques.

Place, publisher, year, edition, pages
Institutionen för datavetenskap, 2005. p. 255
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 945
Keywords
Datavetenskap, system-on-chip, test generation, BIST, hybrid BIST, high-level test, Datavetenskap
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-2994 (URN)91-85297-97-6 (ISBN)
Public defence
2005-05-20, 13:15 (English)
Supervisors
Available from: 2005-07-19 Created: 2005-07-19 Last updated: 2018-01-13
He, Z., Jervan, G., Eles, P. I. & Peng, Z. (2005). Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. In: 8th Euromicro Conference on Digital System Design DSD2005,2005: . Paper presented at 8th Euromicro Conference on Digital System Design DSD2005 (pp. 83). Porto, Portugal: IEEE Computer Society Press
Open this publication in new window or tab >>Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
2005 (English)In: 8th Euromicro Conference on Digital System Design DSD2005,2005, Porto, Portugal: IEEE Computer Society Press , 2005, p. 83-Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detected. We employ the defect probabilities of individual cores to guide the scheduling, such that the expected total test time is minimized and the peak power constraint is satisfied. Based on a hybrid BIST architecture where a combination of deterministic and pseudorandom test sequences is used, the power-constrained test scheduling problem can be formulated as an extension of the two-dimensional rectangular packing problem and a heuristic has been proposed to calculate the near optimal order of different test sequences. The method is also generalized for both test-per-clock and test-per-scan approaches. Experimental results have shown that the proposed heuristic is efficient to find a near optimal test schedule with a low computation overhead.

Place, publisher, year, edition, pages
Porto, Portugal: IEEE Computer Society Press, 2005
Keywords
testing, power optimization, system-on-chip, built-in self-test, BIST, abort-on-fail
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-28507 (URN)10.1109/DSD.2005.63 (DOI)13656 (Local ID)0-7695-2433-8 (ISBN)13656 (Archive number)13656 (OAI)
Conference
8th Euromicro Conference on Digital System Design DSD2005
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2018-01-13
Jervan, G., Ubar, R., Peng, Z. & Eles, P. I. (2005). Test Generation: A Hierarchical Approach. In: M. Sonza Reorda, Z. Peng, M. Violante (Ed.), System-level Test and Validation of Hardware/Software Systems: (pp. 67-81). Berlin: Springer Berlin Heidelberg
Open this publication in new window or tab >>Test Generation: A Hierarchical Approach
2005 (English)In: System-level Test and Validation of Hardware/Software Systems / [ed] M. Sonza Reorda, Z. Peng, M. Violante, Berlin: Springer Berlin Heidelberg , 2005, p. 67-81Chapter in book (Other academic)
Abstract [en]

New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue. This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing errors; design for testability.

Place, publisher, year, edition, pages
Berlin: Springer Berlin Heidelberg, 2005
Series
Springer Series in Advanced Microelectronics ; 17
Keywords
testing, hierachical testing
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-28501 (URN)13650 (Local ID)1-85233-899-7 (ISBN)978-1-84628-145-7 (ISBN)13650 (Archive number)13650 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2018-01-13Bibliographically approved
Jervan, G., Peng, Z., Ubar, R. & Korelina, O. (2004). An Improved Estimation Methodology for Hybrid BIST Cost Calculation. In: IEEE Norchip 2004,2004: . Paper presented at IEEE Norchip 2004 (pp. 297-300).
Open this publication in new window or tab >>An Improved Estimation Methodology for Hybrid BIST Cost Calculation
2004 (English)In: IEEE Norchip 2004,2004, 2004, p. 297-300Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an improved estimation methodology for hybrid BIST cost calculation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is largely determined by the ratio of those test patterns in the final test set. Unfortunately exact algorithms for finding the test sets are computationally very expensive. Therefore in this paper we propose an improved estimation methodology for fast calculation of the hybrid test set. The methodology is based on real fault simulation results and experimental results have shown that the method is more accurate than the statistical method proposed earlier.

Keywords
BIST, testing, cost calculation
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-23197 (URN)10.1109/NORCHP.2004.1423882 (DOI)2608 (Local ID)0-7803-8510-1 (ISBN)2608 (Archive number)2608 (OAI)
Conference
IEEE Norchip 2004
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
Ubar, R., Jenihhin, M., Jervan, G. & Peng, Z. (2004). An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture. In: The 5th IEEE Latin-American Test Workshop,2004 (pp. 98-103).
Open this publication in new window or tab >>An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture
2004 (English)In: The 5th IEEE Latin-American Test Workshop,2004, 2004, p. 98-103Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an approach to the test time minimization problem for parallel hybrid BIST with test pattern broadcasting in core-based systems. The hybrid test set is assembled from pseudorandom test patterns that are generated online and deterministic test patterns that are generated off-line and stored in the system. The pseudorandom patterns are broadcasted and applied to all cores in parallel. The deterministic patterns are, on the other hand, generated for particular cores, one at a time, but applied (broadcasted) in parallel to all other cores and used for the rest of the system as pseudorandom patterns. We propose an iterative algorithm to find the optimal combination between those two test sets under given memory constraints, so that the systems testing time is minimized. Our approach employs a fast cost estimation method in order to avoid exhaustive search and to speed-up the optimization process. Experimental results have shown the efficiency of the algorithm to find a near-optimal solution with very few iterations.

Keywords
testing, hybrid BIST, pseudorandom patterns, deterministic patterns, test pattern broadcasting, core-based systems
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-23285 (URN)2711 (Local ID)2711 (Archive number)2711 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
Ubar, R., Jenihhin, M., Jervan, G. & Peng, Z. (2004). Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. In: The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004,2004: . Paper presented at The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004.
Open this publication in new window or tab >>Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting
2004 (English)In: The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004,2004, 2004Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a technique for hybrid BIST time optimization for testing core-based systems that use test pattern broadcasting for both pseudorandom and deterministic patterns. First we formulate the test time minimization problem for such an architecture. Thereafter we present algorithms for finding an efficient combination of pseudorandom and deterministic test sets under given memory constraints, so that the system testing time can be shortened. We also analyze the significance of the pseudorandom sequence quality for the final results. The results are illustrated and the efficiency of the approach is demonstrated by experimental results.

Keywords
hybrid BIST, test pattern broadcasting, pseudorandom pattern, deterministic pattern, testing
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-23292 (URN)10.1109/DELTA.2004.10057 (DOI)2718 (Local ID)0-7695-2081-2 (ISBN)2718 (Archive number)2718 (OAI)
Conference
The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
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