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Andrei, Alexandru
Publications (10 of 21) Show all publications
Bao, M., Andrei, A., Ion Eles, P. & Peng, Z. (2012). Temperature-Aware Idle Time Distribution for Leakage Energy Optimization. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 20(7), 1187-1200
Open this publication in new window or tab >>Temperature-Aware Idle Time Distribution for Leakage Energy Optimization
2012 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 20, no 7, p. 1187-1200Article in journal (Refereed) Published
Abstract [en]

Large-scale integration with deep sub-micron technologies has led to high power densities and high chip working temperatures. At the same time, leakage energy has become the dominant energy consumption source of circuits due to reduced threshold voltages. Given the close interdependence between temperature and leakage current, temperature has become a major issue to be considered for power-aware system level design techniques. In this paper, we address the issue of leakage energy optimization through temperature aware idle time distribution (ITD). We first propose an offline ITD technique to optimize leakage energy consumption, where only static idle time is distributed. To account for the dynamic slack, we then propose an online ITD technique where both static and dynamic idle time are considered. To improve the efficiency of our ITD techniques, we also propose an analytical temperature analysis approach which is accurate and, yet, sufficiently fast to be used inside the energy optimization loop.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-69730 (URN)10.1109/TVLSI.2011.2157542 (DOI)000305181800004 ()
Available from: 2011-08-01 Created: 2011-08-01 Last updated: 2019-01-28
Andrei, A., Eles, P. I., Jovanovic, O., Schmitz, M., Ogniewski, J. & Peng, Z. (2011). Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 19(1), 10-23
Open this publication in new window or tab >>Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
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2011 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, ISSN 1063-8210, Vol. 19, no 1, p. 10-23Article in journal (Refereed) Published
Abstract [en]

Supply voltage scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the voltage and performance settings according to the application needs. In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the voltage (performance) settings during runtime, i.e., online. However, optimal voltage scaling algorithms are computationally expensive, and thus, if used online, significantly hamper the possible energy savings. To overcome the online complexity, we propose a quasi-static voltage scaling scheme, with a constant online time complexity O(1). This allows to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the voltage settings.

Place, publisher, year, edition, pages
IEEE, 2011
Keywords
Clocks, Complexity theory, Energy minimization, Optimization, Program processors, Runtime, Table lookup, Time frequency analysis, online voltage scaling, quasi-static voltage scaling (QSVS), real-time systems, voltage scaling
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-59628 (URN)10.1109/TVLSI.2009.2030199 (DOI)000285844200002 ()
Note
©2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Alexandru Andrei, Petru Ion Eles, Olivera Jovanovic, Marcus Schmitz, Jens Ogniewski and Zebo Peng, Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints, 2010, IEEE Transactions on Very Large Scale Integration (vlsi) Systems, (19), 1, 10-23. http://dx.doi.org/10.1109/TVLSI.2009.2030199 Available from: 2010-09-22 Created: 2010-09-22 Last updated: 2017-12-12
Rosén, J., Andrei, A., Eles, P. I. & Peng, Z. (2010). Predictable Multiprocessor Systems. In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed).
Open this publication in new window or tab >>Predictable Multiprocessor Systems
2010 (English)In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-59637 (URN)
Available from: 2010-09-22 Created: 2010-09-22 Last updated: 2010-09-27
Bao, M., Andrei, A., Ion Eles, P. & Peng, Z. (2010). Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling. In: Proceedings -Design, Automation and Test in Europe, DATE: . Paper presented at Design, Automation and Test in Europe Conference and Exhibition, DATE 2010; Dresden; Germany (pp. 21-26). IEEE
Open this publication in new window or tab >>Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling
2010 (English)In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2010, p. 21-26Conference paper, Published paper (Refereed)
Abstract [en]

With new technologies, temperature has become a major issue to be considered at system level design. In this paper we propose a temperature aware idle time distribution technique for energy optimization with dynamic voltage scaling (DVS). A temperature analysis approach is also proposed which is accurate and, yet, sufficiently fast to be used inside the optimization loop for idle time distribution and voltage selection.

Place, publisher, year, edition, pages
IEEE, 2010
Series
Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591, E-ISSN 1558-1101
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-59106 (URN)10.1109/DATE.2010.5457241 (DOI)978-3-9810801-6-2 (ISBN)978-1-4244-7054-9 (ISBN)
Conference
Design, Automation and Test in Europe Conference and Exhibition, DATE 2010; Dresden; Germany
Available from: 2010-09-20 Created: 2010-09-09 Last updated: 2019-01-28
Bao, M., Andrei, A., Eles, P. & Peng, Z. (2009). An Energy Efficient Technique for Temperature-Aware Voltage Selection. Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>An Energy Efficient Technique for Temperature-Aware Voltage Selection
2009 (English)Report (Other academic)
Abstract [en]

High power densities in current SoCs result in both huge energy consumption and increased chip temperature. This paper proposes a temperature-aware dynamic voltage selection technique for energy minimization and presents a thorough analysis of the parameters that influence the potential gains that can be expected from such a technique, compared to a voltage selection approach that ignores temperature. In addition to demonstrating the actual percentages of energy that can be saved by being temperature aware, we explore some significant issues in this context, such as the relevance of taking into consideration transient temperature effects at optimization, the impact of the percentage of leakage power relative to the total power consumed and of the degree to which leakage depends on temperature.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2009. p. 7
Series
Technical reports in Computer and Information Science, ISSN 1654-7233 ; 4
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-58012 (URN)
Available from: 2010-07-16 Created: 2010-07-16 Last updated: 2019-01-28Bibliographically approved
Bao, M., Andrei, A., Eles, P. I. & Peng, Z. (2009). On-line Thermal Aware Dynamic Voltage Scaling for Energy Optimization with Frequency/Temperature Dependency Consideration. In: DAC '09 Proceedings of the 46th Annual Design Automation Conference: . Paper presented at 2009 46th ACM/IEEE Design Automation Conference, DAC 2009; San Francisco, CA; United States (pp. 490-495). IEEE Computer Society
Open this publication in new window or tab >>On-line Thermal Aware Dynamic Voltage Scaling for Energy Optimization with Frequency/Temperature Dependency Consideration
2009 (English)In: DAC '09 Proceedings of the 46th Annual Design Automation Conference, IEEE Computer Society, 2009, p. 490-495Conference paper, Published paper (Refereed)
Abstract [en]

With new technologies, temperature has become a major issue to be considered at system level design. Without taking temperature aspects into consideration, no approach to energy or/and performance optimization will be sufficiently accurate and efficient. In this paper we propose an on-line temperature aware dynamic voltage and frequency scaling (DVFS) technique which is able to exploit both static and dynamic slack. The approach implies an offline temperature aware optimization step and on-line voltage/frequency settings based on temperature sensor readings. Most importantly, the presented approach is aware of the frequency/temperature dependency, by which important additional energy savings are obtained.

Place, publisher, year, edition, pages
IEEE Computer Society, 2009
Series
ACM / IEEE Design Automation Conference. Proceedings, ISSN 0738-100X
Keywords
temperature dependency; energy; voltage/frequency scaling
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-58242 (URN)10.1145/1629911.1630039 (DOI)000279394200099 ()978-1-60558-497-3 (ISBN)
Conference
2009 46th ACM/IEEE Design Automation Conference, DAC 2009; San Francisco, CA; United States
Available from: 2010-08-10 Created: 2010-08-09 Last updated: 2014-09-05
Ruggiero, M., Bertozzi, D., Benini, L., Milano, M. & Andrei, A. (2009). Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(3), 378-391
Open this publication in new window or tab >>Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms
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2009 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 28, no 3, p. 378-391Article in journal (Refereed) Published
Abstract [en]

This paper proposes a novel approach to solve the allocation and scheduling problems for variable voltage/frequency multiprocessor systems-on-chip, which minimizes overall system energy dissipation. The optimality of derived system configurations is guaranteed, while the computation efficiency of the optimizer allows for solving problem instances that were traditionally considered beyond reach for exact solvers (optimality gap). Furthermore, this paper illustrates the development- and run-time software infrastructures that assist the user in developing applications and implementing optimizer solutions. The proposed approach guarantees a high level of power, performance, and constraint satisfaction predictability as from validation on the target platform, thus bridging the abstraction gap.

Keywords
Allocation, Benders decomposition, multiprocessor systems-on-chip (MPSoCs), scheduling, virtual platform
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-17286 (URN)10.1109/TCAD.2009.2013536 (DOI)
Available from: 2009-03-16 Created: 2009-03-16 Last updated: 2017-12-13
Andrei, A., Eles, P. I., Peng, Z. & Rosén, J. (2008). Predictable Implementation of Real-Time Applications on Multiprocessor Systems on Chip. In: VLSI Design, 2008. VLSID 2008: . Paper presented at 21st International Conference on VLSI Design (VLSID 2008), 4-8 January 2008, Hyderabad, India (pp. 103-110). IEEE Computer Society
Open this publication in new window or tab >>Predictable Implementation of Real-Time Applications on Multiprocessor Systems on Chip
2008 (English)In: VLSI Design, 2008. VLSID 2008, IEEE Computer Society, 2008, p. 103-110Conference paper, Published paper (Refereed)
Abstract [en]

Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restrictive and particular contexts. One important aspect that makes the analysis difficult is the estimation of the system-s communication behavior. The traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. As opposed to the analysis performed for a single processor system, where the cache miss penalty is constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks- WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this context, we propose, for the first time, an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures.

Place, publisher, year, edition, pages
IEEE Computer Society, 2008
Series
International Conference on VLSI Design. Proceedings, ISSN 1063-9667
Keywords
embedded systems, worst-case execution time analysis, WCET, distributed systems, system-on-chip, SOC, scheduling
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-39303 (URN)10.1109/VLSI.2008.33 (DOI)000253939700024 ()47838 (Local ID)0-7695-3083-4 (ISBN)978-0-7695-3083-3 (ISBN)47838 (Archive number)47838 (OAI)
Conference
21st International Conference on VLSI Design (VLSID 2008), 4-8 January 2008, Hyderabad, India
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-13
Bao, M., Andrei, A., Eles, P. I. & Peng, Z. (2008). Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling. In: 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008. Paper presented at 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008), 16-18 April 2008, Bratislava, Slovakia (pp. 44-49). IEEE Computer Society
Open this publication in new window or tab >>Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling
2008 (English)In: 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, IEEE Computer Society, 2008, p. 44-49Conference paper, Published paper (Refereed)
Abstract [en]

Temperature has become an important issue in nowadays MPSoCs design due to the ever increasing power densities and huge energy consumption. This paper proposes a temperature-aware task mapping technique for energy optimization in systems with dynamic voltage selection capability. It evaluates the efficiency of this technique, based on the analysis of the factors that can influence the potential gains that can be expected from such a technique, compared to a task mapping approach that ignores temperature.

Place, publisher, year, edition, pages
IEEE Computer Society, 2008
Keywords
embedded systems, energy optimization, temperature reduction, mapping, dynamic voltage selection
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-42251 (URN)10.1109/DDECS.2008.4538754 (DOI)000256936300011 ()62035 (Local ID)978-1-4244-2276-0 (ISBN)e-978-1-4244-2277-7 (ISBN)62035 (Archive number)62035 (OAI)
Conference
11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008), 16-18 April 2008, Bratislava, Slovakia
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2019-01-28
Bao, M., Andrei, A., Eles, P. I. & Peng, Z. (2008). Temperature-Aware Voltage Selection for Energy Optimization. In: Design, Automation and Test in Europe, 2008. Paper presented at Design, Automation and Test in Europe (DATE 2008), 10-14 March 2008, Munich, Germany (pp. 1083-1086). IEEE
Open this publication in new window or tab >>Temperature-Aware Voltage Selection for Energy Optimization
2008 (English)In: Design, Automation and Test in Europe, 2008, IEEE , 2008, p. 1083-1086Conference paper, Published paper (Refereed)
Abstract [en]

This paper proposes a temperature-aware dynamic voltage selection technique for energy minimization and presents a thorough analysis of the parameters that influence the potential gains that can be expected from such a technique, compared to a voltage selection approach that ignores temperature.

Place, publisher, year, edition, pages
IEEE, 2008
Series
Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
Keywords
embedded systems, voltage selection, power optimization, temperature variations, leakage
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-39640 (URN)10.1109/DATE.2008.4484920 (DOI)000257940700257 ()50432 (Local ID)978-3-9810801-3-1 (ISBN)e-978-3-9810801-4-8 (ISBN)50432 (Archive number)50432 (OAI)
Conference
Design, Automation and Test in Europe (DATE 2008), 10-14 March 2008, Munich, Germany
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2019-01-28
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