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Andersson, Ola
Publications (10 of 17) Show all publications
Andersson, O. & Vesterbacka, M. (2005). A yield-enhancement strategy for binary-weighted DACs. In: Proc. European Conf. Circuit Theory and Design 2005, ECCTD'05 (pp. 55-58).
Open this publication in new window or tab >>A yield-enhancement strategy for binary-weighted DACs
2005 (English)In: Proc. European Conf. Circuit Theory and Design 2005, ECCTD'05, 2005, , p. 55-58p. 55-58Conference paper, Published paper (Refereed)
Abstract [en]

One of the major contributors to the static nonlinearity of a current-steering digital-to-analog converter (DAC) is mismatch between current sources. A technique for enhancing the yield of binary-weighted current-steering DACs is proposed. The technique utilizes a special case of a general technique for spectral shaping of DAC nonlinearity errors presented earlier and requires oversampling. The technique relies on two DAC models with low computational complexity that can be integrated with the DAC at a negligible cost in terms of area and power consumption. Behavioral-level simulation results indicate that the proposed method has a good potential of enhancing the yield of binary-weighted DACs for situations where the matching errors constitute the dominating source of nonlinearity.

Publisher
p. 55-58
Keywords
digital-analog conversion, sampling methods
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-37344 (URN)10.1109/ECCTD.2005.1522908 (DOI)34745 (Local ID)0-7803-9066-0 (ISBN)34745 (Archive number)34745 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-14
Andersson, O. (2005). Modeling and Implementation of Current-Steering Digital-to-Analog Converters. (Doctoral dissertation). : Institutionen för systemteknik
Open this publication in new window or tab >>Modeling and Implementation of Current-Steering Digital-to-Analog Converters
2005 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications.

Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work.

Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source.

The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations.

It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given.

Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2005. p. 184
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 944
Keywords
Data converter, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), transistor
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-5062 (URN)91-8529-796-8 (ISBN)
Public defence
2005-05-19, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2005-05-30 Created: 2005-05-30 Last updated: 2009-02-12
Säll, E., Andersson, O. & Vesterbacka, M. (2004). A dynamic element matching technique for flash analog-to-digital converters. In: Proc. 8th Nordic Signal Processing Symp., NORSIG'04 (pp. 137-140).
Open this publication in new window or tab >>A dynamic element matching technique for flash analog-to-digital converters
2004 (English)In: Proc. 8th Nordic Signal Processing Symp., NORSIG'04, 2004, p. 137-140Conference paper, Published paper (Refereed)
Abstract [en]

A flash analog-to-digital converter is proposed that employs a new dynamic element matching architecture. The architecture uses a new strategy of incorporating switches in the voltage reference generator that allows lower hardware complexity and higher conversion speed than comparable converters. The converter has been modeled and simulated on a behavioral level in Matlab. The results indicate good linearity properties that together with the expected speed performance should make it suitable in intended communications applications.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-23651 (URN)3145 (Local ID)951-22-7065-X (ISBN)3145 (Archive number)3145 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2009-10-14
Andersson, O. & Vesterbacka, M. (2004). A parameterized cell-based design approach for digital-to-analog converters. In: Proc. IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04 (pp. 225-228).
Open this publication in new window or tab >>A parameterized cell-based design approach for digital-to-analog converters
2004 (English)In: Proc. IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04, 2004, p. 225-228Conference paper, Published paper (Refereed)
Abstract [en]

Due to the lack of proper design automation tools, designers are often forced to use full-custom design methodologies when designing analog and mixed-signal circuits. In this work, we discuss a design methodology based on parameterized cells intended for efficient design. The methodology is illustrated with the design of a 12-bit configurable current-steering DAC. Because the cells are parameterized, their layout must be described in a generalized way, resulting in a longer design time compared with a manual layout of a fixed circuit. However, the parameterized approach simplifies iteration of the layout process and block reuse.

Keywords
digital-analog conversion, integrated circuit layout, mixed analog-digital integrated circuits
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-23645 (URN)3138 (Local ID)0-7695-2182-7 (ISBN)3138 (Archive number)3138 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2009-10-15
Säll, E., Vesterbacka, M. & Andersson, O. (2004). A study of digital decoders in flash analog-to-digital converters. In: Proc. IEEE Int. Symp. Circuits Syst., ISCAS'04 (pp. I-129-I-132).
Open this publication in new window or tab >>A study of digital decoders in flash analog-to-digital converters
2004 (English)In: Proc. IEEE Int. Symp. Circuits Syst., ISCAS'04, 2004, p. I-129-I-132Conference paper, Published paper (Refereed)
Keywords
analog-digital conversion, comparators (circuits), decoding, error correction, error statistics
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-23665 (URN)3160 (Local ID)0-7803-8251-X (ISBN)3160 (Archive number)3160 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2009-10-14
Andersson, O. & Vesterbacka, M. (2004). A testbed for different codes in digital-to-analog converters. In: Proc. Swedish System-on-Chip Conf. 2004, SSoCC'04.
Open this publication in new window or tab >>A testbed for different codes in digital-to-analog converters
2004 (English)In: Proc. Swedish System-on-Chip Conf. 2004, SSoCC'04, 2004Conference paper, Published paper (Other academic)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-23629 (URN)3121 (Local ID)3121 (Archive number)3121 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2009-10-15
Andersson, O. & Vesterbacka, M. (2004). Dynamic element matching in decomposed digital-to-analog converters. In: Proc. IEEE NORCHIP'04 (pp. 187-190). Denmark: TechnoData A/S
Open this publication in new window or tab >>Dynamic element matching in decomposed digital-to-analog converters
2004 (English)In: Proc. IEEE NORCHIP'04, Denmark: TechnoData A/S , 2004, , p. 187-190p. 187-190Conference paper, Published paper (Refereed)
Abstract [en]

A dynamic element matching (DEM) technique is proposed that aims at improving the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) implemented with a decomposed architecture. The architecture consists of a number of small binary-weighted DACs that are controlled such that only a minimum number of unit current sources are switching for the most critical code transitions. The DEM is obtained by scrambling bit pairs with equal weight. In contrast to most other DEM techniques, the scrambling is performed conditionally so that the number of switching current sources does not increase compared with the unscrambled case. Hence, the good glitch properties of the decomposed converter architecture are maintained. Simulations on a behavioral level of some decomposed DACs have been performed. Assuming random uncorrelated matching errors with Gaussian distribution and a 5% standard deviation, the SFDR value giving 90% yield is increased with 5.6 dB for a 14-bit DAC using scrambling of the two bit pairs with the largest weights. The hardware cost for the required scrambling circuits should be low since only two pairs of bits are scrambled.

Place, publisher, year, edition, pages
Denmark: TechnoData A/S, 2004. p. 187-190
Keywords
NORCHIP'04
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-34559 (URN)10.1109/NORCHP.2004.1423854 (DOI)21816 (Local ID)0-7803-8510-1 (ISBN)21816 (Archive number)21816 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-14
Andersson, O. & Vesterbacka, M. (2004). Partial decomposition of digital-to-analog converters. In: Proc. 12th IEEE Mediterranean Electrotechnical Conf., MELECON'04 (pp. 193-196).
Open this publication in new window or tab >>Partial decomposition of digital-to-analog converters
2004 (English)In: Proc. 12th IEEE Mediterranean Electrotechnical Conf., MELECON'04, 2004, p. 193-196Conference paper, Published paper (Refereed)
Abstract [en]

The decomposed DAC architecture was recently proposed as an alternative to the traditional segmented architecture. In this work, we present a modified version of the decomposed architecture with reduced hardware complexity denoted the partially decomposed architecture. Behavioral-level simulations indicate that the partially decomposed architecture is a good alternative for signals with Gaussian distribution, whereas the original decomposed or segmented architectures are preferred for sinusoidal signals.

Keywords
decomposed DAC, circuit layout, digital-analog conversion
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-23667 (URN)10.1109/MELCON.2004.1346806 (DOI)3162 (Local ID)0-7803-8271-4 (ISBN)3162 (Archive number)3162 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2009-10-14
Andersson, O., Andersson, N., Vesterbacka, M. & Wikner, J. (2003). A 14-Bit dual current-steering DAC. In: Proc. Swedish System-on-Chip Conf., SSoCC'03.
Open this publication in new window or tab >>A 14-Bit dual current-steering DAC
2003 (English)In: Proc. Swedish System-on-Chip Conf., SSoCC'03, 2003Conference paper, Published paper (Other academic)
Abstract [en]

A 14-bit dual current-steering digital-to-analog converter implemented in a 0.25 µm CMOS process is presented in this work. Both implementation issues and measurement results are presented. The measured spurious-free dynamic range is higher than 73 dB for signal frequencies up to 3 MHz, and a measured multi-tone power ratio of approximately 71 dB is reported for an ADSL-like input.

Keywords
digital-analog conversion, glitches, nonlinearities
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-50929 (URN)
Available from: 2009-10-15 Created: 2009-10-15 Last updated: 2009-10-17
Andersson, O., Andersson, N., Vesterbacka, M. & Wikner, J. (2003). A method of segmenting digital-to-analog converters. In: Proc. IEEE Southwest Symposium on Mixed-Signal Design, SSMSD'03 (pp. 32-37).
Open this publication in new window or tab >>A method of segmenting digital-to-analog converters
2003 (English)In: Proc. IEEE Southwest Symposium on Mixed-Signal Design, SSMSD'03, 2003, p. 32-37Conference paper, Published paper (Refereed)
Abstract [en]

Segmented architectures are often used in digital-to-analog converters (DACs). Here we propose a DAC structure based on recursive decomposition of an N-bit binary DAC into two (N-1) bit DACs and one 1 bit DAC. A DAC model that includes matching errors has been simulated. The simulation results indicate that by using four layers of decomposition it is possible to achieve similar performance as when using seven bits of traditional segmentation.

Keywords
circuit simulation, digital-analog conversion, network synthesis
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-50931 (URN)10.1109/SSMSD.2003.1190392 (DOI)0-7803-7778-8 (ISBN)
Available from: 2009-10-15 Created: 2009-10-15 Last updated: 2009-10-17
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