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Säll, Erik
Publications (10 of 16) Show all publications
Säll, E. (2007). Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator CMOS Technology. (Doctoral dissertation). : Institutionen för systemteknik
Open this publication in new window or tab >>Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator CMOS Technology
2007 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivator for using the SOI CMOS technology instead of bulk CMOS seems to be the smaller gate leakage power consumption.

The targeted applications in mind for the ADCs are read channel and ultra wideband radio applications. These applications requires a resolution of at least four to six bits and a sampling frequency of above 1 GHz. Hence the flash ADC topology is chosen for the implementations. In this work we do also propose enhancements to the flash ADC converter. Further, this work also investigates introduction of dynamic element matching (DEM) into a flash ADC. A method to introduce DEM into the reference net of a flash ADC is proposed and evaluated.

To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a top-down design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level using MATLAB and SpectreHDL. The modeling results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.

The first flash ADC implementation has a conventional topology. It has a resistor net connected to a number of latched comparators and employs a ones-counter thermometer-to-binary decoder. This ADC serves as a reference for evaluating the other topologies. The measurements indicate a maximum sampling frequency of 470 MHz, an SNDR of 26.3 dB, and an SFDR of about 29 to 35 dB.

The second ADC has a similar topology as the reference ADC, but its thermometer-to-binary decoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact decoder with a regular structure and a short critical path. The measurements show that it is more efficient in terms of power consumption than the ones-counter decoder and it has 40 % smaller chip area. Further, the SNDR and SFDR are similar as for the reference ADC, but its maximum sampling frequency is about 660 MHz.

The third ADC demonstrates the introduction of DEM into the reference net of a flash ADC. Our proposed technique requires fewer switches in the reference net than other proposals. Our technique should thereby be able to operate at higher sampling and input frequencies than compared with the other proposals. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB in average when introducing DEM. The transistor level simulations in Cadence and measurements of the ADC with DEM indicates that the SFDR improves by 6 dB and 1.5 dB, respectively, when applying DEM. The smaller improvement indicated by the measurements is believed to be due to a design flaw discovered during the measurements. A mask layer for the resistors of the reference net is missing, which affects their accuracy and degrades the ADC performance. The same reference net is used in the other ADCs, and therefore degrades their performance as well. Hence the measured performance is significantly lower than indicated by the transistor level simulations. Further, it is observed that the improved SFDR is traded for an increased chip area and a reduction of the maximum sampling frequency. The DEM circuitry impose a 30 % larger chip area.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2007. p. 173
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1093
Keywords
analog-to-digital converters, ADC, silicon-on-insulator, SOI
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-8712 (URN)978-91-85715-18-3 (ISBN)
Public defence
2007-05-11, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2007-05-02 Created: 2007-05-02 Last updated: 2009-03-12
Säll, E. & Vesterbacka, M. (2007). Thermometer-to-binary decoders for flash analog-to-digital converters. In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07 (pp. 240-243).
Open this publication in new window or tab >>Thermometer-to-binary decoders for flash analog-to-digital converters
2007 (English)In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07, 2007, p. 240-243Conference paper, Published paper (Refereed)
Abstract [en]

Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.

Keywords
CMOS integrated circuits, analog-digital conversion, decoding, error correction, silicon-on-insulator
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-50933 (URN)10.1109/ECCTD.2007.4529581 (DOI)21519 (Local ID)978-1-4244-1341-6 (ISBN)21519 (Archive number)21519 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-15
Säll, E. & Vesterbacka, M. (2006). 6-bit flash ADC with dynamic element matching. In: Proc. IEEE 24th Norchip Conf., NORCHIP'06 (pp. 159-162).
Open this publication in new window or tab >>6-bit flash ADC with dynamic element matching
2006 (English)In: Proc. IEEE 24th Norchip Conf., NORCHIP'06, 2006, , p. 159-162p. 159-162Conference paper, Published paper (Refereed)
Abstract [en]

Previous work have suggested approaches to introduce dynamic element matching (DEM) into the reference net of a flash analog-to-digital converter. No implementations of such circuits have however been reported. In this work the authors evaluate the suitability and estimate the performance enhancements of a recently proposed DEM architecture by using this in the design of a 6-bit Nyquist rate converter. The converter is sent for manufacturing in a 130 nm partially depleted silicon-on-insulator CMOS technology. It was simulated at transistor level in Cadence using the foundry provided BSIM3SOI Eldo models. These simulations yield a maximum sampling frequency of at least 350 MHz. The simulations also indicate a performance improvement in terms of spurious free dynamic range when using dynamic element matching.

Publisher
p. 159-162
Keywords
CMOS integrated circuits, analog-digital conversion, integrated circuit modeling, silicon-on-insulator
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-35796 (URN)10.1109/NORCHP.2006.329268 (DOI)28599 (Local ID)1-4244-0772-9 (ISBN)28599 (Archive number)28599 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-14
Backenius, E., Säll, E. & Gustafsson, O. (2006). Bidirectional Conversion to Minimum Signed-Digit Representation. In: Circuits and Systems, 2006. ISCAS 2006.: .
Open this publication in new window or tab >>Bidirectional Conversion to Minimum Signed-Digit Representation
2006 (English)In: Circuits and Systems, 2006. ISCAS 2006., 2006Conference paper, Published paper (Other academic)
Abstract [en]

In this work an approach to converting a number in two's complement representation to a minimum signed-digit representation is proposed. The novelty in this work is that this conversion is done from left-to-right and right-to-left concurrently. Hence, the execution time is significantly decreased, while the area overhead is small.

Keywords
Boolean functions, digital arithmetic, bidirectional conversion, signed-digit representation
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14450 (URN)10.1109/ISCAS.2006.1693109 (DOI)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2015-03-11
Backenius, E., Säll, E., Andersson, O. & Vesterbacka, M. (2006). Programmable reference generator for on-chip measurement. In: Proc. 24th IEEE Norchip Conf., NORCHIP'06 (pp. 89-92).
Open this publication in new window or tab >>Programmable reference generator for on-chip measurement
2006 (English)In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 89-92Conference paper, Published paper (Refereed)
Abstract [en]

In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

Keywords
comparators, digital-analog conversion, electric noise measurement, integrated circuit measurement, integrated circuit noise, programmable circuits, reference circuits
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14448 (URN)10.1109/NORCHP.2006.329251 (DOI)1-4244-0772-9 (ISBN)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
Säll, E. & Vesterbacka, M. (2005). 6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications. In: Proc. European Conf. on Circuit Theory and Design, ECCTD'05 (pp. I/127-I/130).
Open this publication in new window or tab >>6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications
2005 (English)In: Proc. European Conf. on Circuit Theory and Design, ECCTD'05, 2005, p. I/127-I/130Conference paper, Published paper (Refereed)
Abstract [en]

The purpose of this work is to investigate the possibility to implement analog base band circuitry along with digital circuitry in silicon-on-insulator technology. Hence a 6 bit Nyquist rate flash analog-to-digital converter is designed in a 130 nm CMOS silicon-on-insulator technology. The converter is aimed for read channel or ultra-wideband radio applications. The simulations indicate a 170 mW power consumption at a maximum sampling rate of 1 GHz. The supply voltage is only 1.2 V. The effective number of bit is 5.8 bit and the effective resolution bandwidth is 390 MHz. An energy per conversion step of 3.9 pJ indicate that this converter is as efficient as other state-of-the-art converters, without using interpolation or averaging techniques.

Keywords
CMOS integrated circuits, UHF integrated circuits, analog-digital conversion, integrated circuit design, silicon-on-insulator, ultra wideband communication
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-34481 (URN)10.1109/ECCTD.2005.1522926 (DOI)21521 (Local ID)0-7803-9066-0 (ISBN)21521 (Archive number)21521 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-14
Säll, E. & Vesterbacka, M. (2005). Comparison of two thermometer-to-binary decoders for high-performance flash ADCs. In: Proc. IEEE 23rd NORCHIP Conf., NORCHIP'05 (pp. 253-256).
Open this publication in new window or tab >>Comparison of two thermometer-to-binary decoders for high-performance flash ADCs
2005 (English)In: Proc. IEEE 23rd NORCHIP Conf., NORCHIP'05, 2005, p. 253-256Conference paper, Published paper (Refereed)
Abstract [en]

The performance of flash analog-to-digital converters is affected significantly by the choice of thermometer-tobinary decoder topology. In this work two different promising decoder topologies, multiplexer-based and onescounter, are evaluated. Two converters with different decoders, but otherwise similar, are therefore designed. Two test chips are also sent for manufacturing in a 130 nm silicon-on-insulator CMOS technology. The converter performance is evaluated by simulations using foundry provided models. The results show that both decoders can be used in high-speed converters, but the ones-counter decoder is more robust and yield a higher converter efficiency.

Keywords
CMOS integrated circuits, analog-digital conversion, binary codes, decoding, integrated circuit design, logic design, silicon-on-insulator
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-34479 (URN)10.1109/NORCHP.2005.1597037 (DOI)21519 (Local ID)1-4244-0064-3 (ISBN)21519 (Archive number)21519 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-14
Säll, E. & Vesterbacka, M. (2005). Design and evaluation of a comparator in CMOS SOI. In: Proc. National Conf. on Radio Science, RVK'05.
Open this publication in new window or tab >>Design and evaluation of a comparator in CMOS SOI
2005 (English)In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper, Published paper (Other academic)
Abstract [en]

The purpose of this work is to find good design techniques for the analog/mixed-signal parts of a system-onchip in SOI. A comparator has therefore been designed and manufactured in a 0.13 um partially depleted SOI CMOS technology. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter, with a sampling frequency of 1.5 GHz, or above. An introduction to the silicon-on-insulator (SOI) technology is also given and some of the major advantages and disadvantages of using SOI are presented.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-34483 (URN)21523 (Local ID)21523 (Archive number)21523 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-14
Säll, E. (2005). Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology. (Licentiate dissertation). : Institutionen för systemteknik
Open this publication in new window or tab >>Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology
2005 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.

To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.

The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.

The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.

A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2005. p. 126
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1213
Keywords
flash analog-to-digital converter, ADC, silicon-on-insulator, SOI, top-down design, dynamic element matching, DEM, thermometer-to-binary encoder, flash ADC modeling
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-5260 (URN)91-85457-79-5 (ISBN)
Presentation
2005-12-21, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Note
Report code: LiU-Tek-Lic-2005:68.Available from: 2005-12-23 Created: 2005-12-23 Last updated: 2009-05-15
Säll, E. & Vesterbacka, M. (2005). Mixed signal design in SOI CMOS technology. In: Proc. Swedish System-on-Chip Conf., SSoCC'05.
Open this publication in new window or tab >>Mixed signal design in SOI CMOS technology
2005 (English)In: Proc. Swedish System-on-Chip Conf., SSoCC'05, 2005Conference paper, Published paper (Other academic)
Abstract [en]

The purpose of this work is to find good design techniques for the analog/mixed-signal parts of a system-on-chip in silicon-on-insulator (SOI). A 6-bit flash analog-to-digital converter (ADC) has therefore been designed and manufactured in a 130 nm partially depleted SOI CMOS technology. The ADC is designed for a sampling frequency of 1.5 GHz or above. An introduction to the SOI technology is also given and some of the major advantages and disadvantages of using SOI are presented.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-34484 (URN)21524 (Local ID)21524 (Archive number)21524 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-14
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