In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5–6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 μm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 29 subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole frontend have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.

A 1.4V wideband inductorless LNA, implemented in a 0.13mum CMOS process, consumes 25mW and occupies 0.019mm². Measurement results show 17dB voltage gain, 7GHz BW, 2.4dB NF at 3GHz, -4.1 dBm IIP3, and -20dBm P_1dB. A common-drain feedback circuit provides wideband 50Omega input matching and partial noise cancellation. A current reuse technique improves both gain and power.

The wireless market is developing very fast today with a steadily increasing number of users all around the world. An increasing number of users and the constant need for higher and higher data rates have led to an increasing number of emerging wireless communication standards. As a result there is a huge demand for flexible and low-cost radio architectures for portable applications. Moving towards multistandard radio, a high level of integration becomes a necessity and can only be accomplished by new improved radio architectures and full utilization of technology scaling. Modern nanometer CMOS technologies have the required performance for making high-performance RF circuits together with advanced digital signal processing. This is necessary for the development of low-cost highly integrated multistandard radios. The ultimate solution for the future is a software-defined radio, where a single hardware is used that can be reconfigured by software to handle any standard. Direct analog-to-digital conversion could be used for that purpose, but is not yet feasible due to the extremely tough requirements that put on the analog-to-digital converter (ADC). Meanwhile, the goal is to create radios that are as flexible as possible with today’s technology. The key to success is to have an RF front-end architecture that is flexible enough without putting too tough requirements on the ADC.

One of the key components in such a radio front-end is a multiband multistandard low-noise amplifier (LNA). The LNA must be capable of handling several carrier frequencies within a large bandwidth. Therefore it is not possible to optimize the circuit performance for just one frequency band as can be done for a single application LNA. Two different circuit topologies that are suitable for multiband multistandard LNAs have been investigated, implemented, and measured. Those two LNA topologies are: (i) wideband LNAs that cover all the frequency bands of interest (ii) tunable narrowband LNAs that are tunable over a wide range of frequency bands.

Before analog-to-digital conversion the RF signal has to be downconverted to a frequency manageable by the analog-to-digital converter. Recently the concept of direct sampling of the RF signal and discrete-time signal processing before analog-to-digital conversion has drawn a lot of attention. Today’s CMOS technologies demonstrate very high speeds, making the RF-sampling technique appealing in a context of multistandard operation at GHz frequencies. In this thesis the concept of RF sampling and decimation is used to implement a flexible RF front-end, where the RF signal is sampled and downconverted to baseband frequency. A discrete-time switched-capacitor filter is used for filtering and decimation in order to decrease the sample rate from a value close to the carrier frequency to a value suitable for analog-to-digital conversion. To demonstrate the feasibility of this approach an RF-sampling front-end primarily intended for WLAN has been implemented in a 0.13 μm CMOS process.