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Dabrowski, Jerzy
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Publications (10 of 87) Show all publications
Qazi, F., Duong, Q.-T. & Dabrowski, J. (2016). Tunable Selective Receiver Front-End with Impedance Transformation Filtering. International journal of circuit theory and applications, 44(5), 1071-1093
Open this publication in new window or tab >>Tunable Selective Receiver Front-End with Impedance Transformation Filtering
2016 (English)In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, no 5, p. 1071-1093Article in journal (Refereed) Published
Abstract [en]

A highly selective impedance transformation filtering technique suitable for tunable selective RF receivers is proposed in this paper. To achieve blocker rejection comparable to SAW filters, we use a two stage architecture based on a low noise trans-conductance amplifier (LNTA). The filter rejection is captured by a linear periodically varying (LPV) model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. This model is also used to estimate “back folding” by interferers placed at harmonic frequencies. Discussed is also the effect of thermal noise folding and phase noise on the circuit noise figure. As a proof of concept a chip design of a tunable RF front-end using 65 nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB,out of bandIIP3 > +17 dBm and blocker P1dB > +5 dBm over frequency range of 0.5—3 GHz.

Place, publisher, year, edition, pages
John Wiley & Sons, 2016
Keywords
SAW-less receiver; N-path filter; wideband selective RF front-end
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:liu:diva-122701 (URN)10.1002/cta.2125 (DOI)000376206000009 ()
Available from: 2015-11-16 Created: 2015-11-16 Last updated: 2017-12-01Bibliographically approved
Duong, Q. T., Qazi, F. & Dabrowski, J. (2015). Analysis and design of low noise transconductance amplifier for selective receiver front-end. Analog Integrated Circuits and Signal Processing, 85(2), 361-372
Open this publication in new window or tab >>Analysis and design of low noise transconductance amplifier for selective receiver front-end
2015 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 85, no 2, p. 361-372Article in journal (Refereed) Published
Abstract [en]

Analysis and design of a low-noise transconductance amplifier (LNTA) aimed at selective current-mode (SAW-less) wideband receiver front-end is presented. The proposed LNTA uses double cross-coupling technique to reduce noise figure (NF), complementary derivative superposition, and resistive feedback to achieve high linearity and enhance input matching. The analysis of both NF and IIP3 using Volterra series is described in detail and verified by SpectreRF (A (R)) circuit simulation showing NF less than 2 dB and IIP3 = 18 dBm at 3 GHz. The amplifier performance is demonstrated in a two-stage highly selective receiver front-end implemented in 65 nm CMOS technology. In measurements the front-end achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 greater than+17 dBm and blocker P-1dB greater than+5 dBm over frequency range of 0.5-3 GHz.

Place, publisher, year, edition, pages
Springer, 2015
Keywords
Low-noise transconductance amplifier (LNTA); Highly linear LNA; Wideband LNA; SAW-less receiver; Wideband selective RF front-end
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-122187 (URN)10.1007/s10470-015-0629-5 (DOI)000361984600014 ()
Available from: 2015-10-26 Created: 2015-10-23 Last updated: 2017-12-01Bibliographically approved
Qazi, F. & Dabrowski, J. (2015). Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study. IEEE Journal of Emerging and Selected Topics in Power Electronics, 5(4), 624-637
Open this publication in new window or tab >>Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study
2015 (English)In: IEEE Journal of Emerging and Selected Topics in Power Electronics, ISSN 2168-6777, E-ISSN 2168-6785, Vol. 5, no 4, p. 624-637Article in journal (Refereed) Published
Abstract [en]

In this paper we study passive switch-capacitor sigma-delta (ΣΔ) modulators suitable for low power applications. Using a one-bit quantizer as the only active block those modulators save power and achieve high linearity. However, their order is largely limited since the passive loop filter presents a significant attenuation to the signal. Typically with a secondorder filter the modulator can achieve a satisfactory signal-toquantization-noise ratio (SQNR) by using a large enough oversampling (OSR) that also creates a tradeoff with the power consumption. A passive ΣΔ modulator when modeled as a linear system requires extraction of the equivalent loop gain. It is shown that for this purpose the quantization and thermal noise should be considered jointly. The paper presents optimization of the modulator in the design space defined by the filter capacitor ratios and the feedback coefficients. Included is a detailedanalysis of the thermal noise, quantization noise, and other parasitic effects. The discussion is supported by 65 nm CMOS chip measurements showing power consumption < 0.62μW, SNDR = 73 dB, and energy efficiency < 0.17 pJ/step.

Place, publisher, year, edition, pages
IEEE Press, 2015
Keywords
Passive sigma-delta modulator, passive SC filter, ADC, CMOS, thermal noise in SC circuit, equivalent quantizer gain
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112881 (URN)10.1109/JETCAS.2015.2502169 (DOI)000367302600013 ()
Note

Vid tiden för disputation förelåg publikationen endast som manuskript

Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2017-12-05
Ramzan, R. & Dabrowski, J. (2015). RF Calibration of On-Chip DfT Chain by DC Stimuli and Statistical Multivariate Regression Technique. Integration, 49, 14-21
Open this publication in new window or tab >>RF Calibration of On-Chip DfT Chain by DC Stimuli and Statistical Multivariate Regression Technique
2015 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 49, p. 14-21Article in journal (Refereed) Published
Abstract [en]

The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a general RF calibration scheme using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error in DfT circuit response can be reduced to 2.5% for input stimuli in excess of 500mV. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging.

Place, publisher, year, edition, pages
Elsevier, 2015
Keywords
DfT, On-chip RF detector, RF BIST, RF calibration, RF DfT, RF testing, ANN application
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-105514 (URN)10.1016/j.vlsi.2014.11.006 (DOI)000351018200002 ()
Available from: 2014-03-25 Created: 2014-03-25 Last updated: 2017-12-05
Qazi, F., Duong, Q.-T. & Dabrowski, J. (2015). Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering. IEEE Transactions on Circuits and Systems - II - Express Briefs, 62(5), 421-425
Open this publication in new window or tab >>Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 5, p. 421-425Article in journal (Refereed) Published
Abstract [en]

In order to achieve blocker rejection comparable to surface acoustic wave (SAW) filters, we propose a two-stage tunable receiver front-end architecture based on impedance frequency transformation and low-noise transconductance amplifier (LNTA) circuits. The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. The effect of thermal noise folding on the circuit noise figure, as well as clock phase mismatch on filter gain are also discussed. As a proof of concept, a chip design of a tunable radio-frequency front end using 65-nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 > +17 dBm and blocker P1 dB > +5 dBm over frequency range of 0.5-3 GHz.

Keywords
SAW-less receiver, N-path filter, wideband selective RF front-end
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112879 (URN)10.1109/TCSII.2014.2385213 (DOI)000353636400001 ()
Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2017-12-05Bibliographically approved
Duong, Q.-T., Dabrowski, J. & Alvandpour, A. (2014). Design and Analysis of High Speed Capacitive Pipeline DACs. Analog Integrated Circuits and Signal Processing, 80(3), 359-374
Open this publication in new window or tab >>Design and Analysis of High Speed Capacitive Pipeline DACs
2014 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 80, no 3, p. 359-374Article in journal (Refereed) Published
Abstract [en]

Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

Keywords
capacitive DAC, high speed DAC, highly linear output driver
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-105516 (URN)10.1007/s10470-014-0350-9 (DOI)000342079400005 ()
Available from: 2014-03-25 Created: 2014-03-25 Last updated: 2019-09-05
Qazi, F. & Dabrowski, J. (2014). Tunable Selective Receiver Front-End with Impedance Transformation Filtering. In: : . Paper presented at Swedish System-on-Chip Conference (SSOCC), 2014.
Open this publication in new window or tab >>Tunable Selective Receiver Front-End with Impedance Transformation Filtering
2014 (English)Conference paper, Published paper (Refereed)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-114754 (URN)
Conference
Swedish System-on-Chip Conference (SSOCC), 2014
Available from: 2015-03-03 Created: 2015-03-03 Last updated: 2015-03-11
Duong, Q.-T. & Dabrowski, J. J. (2013). Focused Calibration for Advanced RF Test with Embedded RF Detectors. In: European Conference on Circuit Theory and Design (ECCTD), 2013: . Paper presented at 21st European Conference on Circuit Theory and Design (ECCTD), September 8-12, Dresden, Germany (pp. 1-4). IEEE
Open this publication in new window or tab >>Focused Calibration for Advanced RF Test with Embedded RF Detectors
2013 (English)In: European Conference on Circuit Theory and Design (ECCTD), 2013, IEEE , 2013, p. 1-4Conference paper, Published paper (Refereed)
Abstract [en]

In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.

Place, publisher, year, edition, pages
IEEE, 2013
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-97268 (URN)10.1109/ECCTD.2013.6662259 (DOI)9783000437854 (ISBN)9783000434303 (ISBN)
Conference
21st European Conference on Circuit Theory and Design (ECCTD), September 8-12, Dresden, Germany
Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2016-01-18Bibliographically approved
Duong, Q.-T., Dabrowski, J. & Alvandpour, A. (2013). Highly linear open-loop output driver design for high speed capacitive DACs. In: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA: . Paper presented at 31st Norchip Conference, 11-12 November 2013, Vilnius, Lithuania (pp. 1-4).
Open this publication in new window or tab >>Highly linear open-loop output driver design for high speed capacitive DACs
2013 (English)In: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA, 2013, p. 1-4Conference paper, Published paper (Refereed)
Abstract [en]

Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-102930 (URN)10.1109/NORCHIP.2013.6702039 (DOI)9781479916474 (ISBN)
Conference
31st Norchip Conference, 11-12 November 2013, Vilnius, Lithuania
Available from: 2014-01-08 Created: 2014-01-08 Last updated: 2019-09-05Bibliographically approved
Ahsan, N., Svensson, C., Ramzan, R., Dąbrowski, J., Ouacha, A. & Samuelsson, C. (2012). A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS. Analog Integrated Circuits and Signal Processing, 70(1), 79-90
Open this publication in new window or tab >>A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS
Show others...
2012 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, p. 79-90Article in journal (Refereed) Published
Abstract [en]

This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

Place, publisher, year, edition, pages
SpringerLink, 2012
Keywords
Blocker suppression, common gate (CG), highly linear, low power, multi-standard, software defined radio, wideband front-end
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18511 (URN)10.1007/s10470-011-9667-9 (DOI)000298604100007 ()
Note
The original status of this article was: Manuscript.Available from: 2009-05-29 Created: 2009-05-29 Last updated: 2017-12-13Bibliographically approved
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