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Fritzin, Jonas
Publications (10 of 31) Show all publications
Johansson, T. & Fritzin, J. (2014). A Review of Watt-Level CMOS RF Power Amplifiers. IEEE transactions on microwave theory and techniques, 62(1), 111-124
Open this publication in new window or tab >>A Review of Watt-Level CMOS RF Power Amplifiers
2014 (English)In: IEEE transactions on microwave theory and techniques, ISSN 0018-9480, E-ISSN 1557-9670, Vol. 62, no 1, p. 111-124Article, review/survey (Refereed) Published
Abstract [en]

This paper reviews the design of watt-level integrated CMOS RF power amplifiers (PAs) and state-of-the-art results in the literature. To reach watt-level output power from a single-chip CMOS PA, two main strategies can be identified: use of high supply voltage and use of matching and power combination. High supply voltage limits are closely related to device design in the fabrication process. However, the maximum operating voltage can be improved by amplifier class selection, circuit solutions, and process modifications or mask changes. High output power can also be reached by the use of on-chip matching and power combination, commonly using on-chip transformers. Reliability often sets the limits for the PA design, and PA degradation mechanisms are reviewed. A compilation of state-of-the-art published results for linear and switched watt-level PAs, as well as a few fully integrated CMOS PAs, is presented and discussed.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2014
Keywords
CMOS power amplifiers (PAs); integration; system-on-chip (SoC)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-104124 (URN)10.1109/TMTT.2013.2292608 (DOI)000329498500014 ()
Available from: 2014-02-07 Created: 2014-02-07 Last updated: 2017-12-06
Raza Khan, H., Fritzin, J., Alvandpour, A. & ul Wahab, Q. (2013). A parallel circuit differential class-E power amplifier using series capacitance. Analog Integrated Circuits and Signal Processing, 75(1), 31-40
Open this publication in new window or tab >>A parallel circuit differential class-E power amplifier using series capacitance
2013 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 75, no 1, p. 31-40Article in journal (Refereed) Published
Abstract [en]

Class-E amplifiers are attractive for wireless handsets because of their high efficiency and simple implementation. However, it requires inductors in its output matching network that are inherently low Q components affecting efficiency and may require significantly large area in fully integrated implementation. In this paper a novel approach of implementing parallel circuit differential class-E amplifier is presented. Instead of using an inductor parallel to the transistor drain of each amplifier, a single capacitor at the single ended side of the balun provides the parallel inductance effect to the switching transistors. As a result, number of inductors required for circuit implementation is reduced which means reduced losses, less area and better tuning of reactance can be achieved. A test circuit is implemented in 0.13 mu m CMOS process. Measurement results verify the validity of the concept. The Power Amplifier achieves 22 dBm output power at 2.4 GHz from a 2.5 V with an overall Power Added Efficiency of 38 %.

Place, publisher, year, edition, pages
Springer Verlag (Germany), 2013
Keywords
Power amplifier, Parallel circuit, Class-E, Lattice L-C balun
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-90745 (URN)10.1007/s10470-013-0036-8 (DOI)000316016100003 ()
Available from: 2013-04-05 Created: 2013-04-05 Last updated: 2019-09-05
Jung, Y., Fritzin, J., Enqvist, M. & Alvandpour, A. (2013). Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 60(7), 1915-1928
Open this publication in new window or tab >>Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS
2013 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 7, p. 1915-1928Article in journal (Refereed) Published
Abstract [en]

This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. Exploring the structure of the outphasing PA, the problem can be reformulated from a nonconvex problem into a convex least-squares problem, and the predistorter can be calculated analytically. The method has been evaluted for 5MHz Wideband Code-Division Multiple Access (WCDMA) and Long Term Evolution (LTE) uplink signals with Peak-to-Average Power Ratio (PAPR) of 3.5 dB and 6.2 dB, respectively, applied to a fully integrated Class-D outphasing RF PA in 65nm CMOS. At 1.95 GHz for a 5.5V supply voltage, the measured output power of the PA was +29.7dBm with a power-added efficiency (PAE) of 26.6 %. For the WCDMA signal with +26.0dBm of channel power, the measured Adjacent Channel Leakage Ratio (ACLR) at 5MHz and 10MHz offsets were -46.3 dBc and -55.6 dBc with predistortion, compared to -35.5 dBc and -48.1 dBc without predistortion. For the LTE signal with +23.3dBm of channel power, the measured ACLR at 5MHz offset was -43.5 dBc with predistortion, compared to -34.1 dBc without predistortion.

Keywords
Outphasing, amplifier, linearization, predistortion, complementary metal-oxide-semiconductor (CMOS)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-71862 (URN)10.1109/TCSI.2012.2230507 (DOI)000322331200020 ()
Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2019-09-05Bibliographically approved
Fritzin, J., Mesgarzadeh, B. & Alvandpour, A. (2012). A Class-D Stage with Harmonic Suppression and DLL-Based Phase Generation. In: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS): . Paper presented at 55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 45-48). Lida Ray Technologies Inc.,
Open this publication in new window or tab >>A Class-D Stage with Harmonic Suppression and DLL-Based Phase Generation
2012 (English)In: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), Lida Ray Technologies Inc., , 2012, p. 45-48Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a Class-D stage with 3rd harmonic suppression operating at 2V(DD) (i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Omega load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.

Place, publisher, year, edition, pages
Lida Ray Technologies Inc.,, 2012
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-96564 (URN)10.1109/MWSCAS.2012.6291953 (DOI)000312667200012 ()978-1-4673-2525-7 (ISBN)978-1-4673-2526-4 (ISBN)
Conference
55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
Available from: 2013-08-21 Created: 2013-08-20 Last updated: 2019-09-05
Fritzin, J., Mesgarzadeh, B. & Alvandpour, A. (2012). A Class-D Stage with Third Harmonic Suppression and DLL-Based Phase Generation. Paper presented at 55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2012), 5-8 August 2012, Boise, Idaho, USA.
Open this publication in new window or tab >>A Class-D Stage with Third Harmonic Suppression and DLL-Based Phase Generation
2012 (English)Conference paper, Published paper (Refereed)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-86343 (URN)
Conference
55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2012), 5-8 August 2012, Boise, Idaho, USA
Available from: 2012-12-13 Created: 2012-12-13 Last updated: 2019-09-05
Johansson, T., Solati, N. & Fritzin, J. (2012). A high-linearity SiGe RF power amplifier for 3G and 4G small basestations. International journal of electronics (Print), 99(8), 1145-1153
Open this publication in new window or tab >>A high-linearity SiGe RF power amplifier for 3G and 4G small basestations
2012 (English)In: International journal of electronics (Print), ISSN 0020-7217, E-ISSN 1362-3060, Vol. 99, no 8, p. 1145-1153Article in journal (Refereed) Published
Abstract [en]

This article presents the design and evaluation of a linear 3.3V SiGe power amplifier for 3G and 4G femtocells with 18dBm modulated output power at 2140 MHz. Different biasing schemes to achieve high linearity with low standby current were studied. The adjacent channel power ratio linearity performance with wide-band code division multiple access (3G) and long term evolution (4G) downlink signals were compared and differences analysed and explained.

Place, publisher, year, edition, pages
Taylor andamp; Francis, 2012
Keywords
power amplifier; WCDMA; LTE; biasing; linearity; ACPR
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-79712 (URN)10.1080/00207217.2011.651695 (DOI)000306287700008 ()
Available from: 2012-08-13 Created: 2012-08-13 Last updated: 2017-12-07
Fritzin, J., Svensson, C. & Alvandpour, A. (2012). Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS. IEEE Transactions on Circuits and Systems - II - Express Briefs, 59(11), 726-730
Open this publication in new window or tab >>Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS
2012 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 59, no 11, p. 726-730Article in journal (Refereed) Published
Abstract [en]

This brief presents the design and analysis of a 5.5-V class-D stage used in two fully integrated watt-level, +32.0 and +29.7 dBm, outphasing RF power amplifiers (PAs) in standard 130- and 65-nm CMOS technologies. The class-D stage utilizes a cascode configuration, driven by an ac-coupled low-voltage driver, to allow a 5.5-V supply in the 1.2-/2.5-V technologies without excessive device voltage stress. The rms electric fields (E) across the gate oxides and the optimal bias point, where the voltage stress is equally divided between the transistors, are computed. At the optimal bias point, the rms E, the power dissipation of the parasitic drain capacitance of the common-source transistors, and the equivalent on-resistances are reduced by approximately 25%, 50%, and 25%, compared to a conventional cascode (inverter) stage. To the authors best knowledge, the class-D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state-of-the-art output power and bandwidth.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2012
Keywords
Amplifier, CMOS, outphasing
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-88467 (URN)10.1109/TCSII.2012.2228391 (DOI)000313426100006 ()
Available from: 2013-02-07 Created: 2013-02-07 Last updated: 2019-09-05
Fritzin, J., Svensson, C. & Alvandpour, A. (2012). Design and Analysis of a Class-D Stage with Harmonic Suppression. Paper presented at EEE Transactions on Circuits and Systems–I: Regular Papers. Transactions on Circuits and Systems–I: Regular Papers, 59(6), 1178-1186
Open this publication in new window or tab >>Design and Analysis of a Class-D Stage with Harmonic Suppression
2012 (English)In: Transactions on Circuits and Systems–I: Regular Papers, ISSN 1549-8328, Vol. 59, no 6, p. 1178-1186Article in journal (Refereed) Published
Abstract [en]

This paper presents the design and analysis of a low-power Class-D stage in 90nm CMOS featuring a harmonic suppression technique, which cancels the 3rd harmonic by shaping the output voltage waveform. Only digital circuits are used and the short-circuit current present in Class-D inverterbased output stages is eliminated, relaxing the buffer requirements. Using buffers with reduced drive strength for the output stage reduces the 5th harmonic at the output, as the rise and fall time of the output voltage increase. Operating at 900MHz, the measured output power was +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% at 1.2V. The 3rd and 5th harmonics were suppressed by 34dB and 4dB, respectively, compared to an inverter-based Class-D stage.1

Place, publisher, year, edition, pages
IEEE, 2012
Keywords
Radio transmitter, CMOS, harmonic rejection
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-71859 (URN)10.1109/TCSI.2011.2173389 (DOI)000304825700004 ()
Conference
EEE Transactions on Circuits and Systems–I: Regular Papers
Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2019-09-05Bibliographically approved
Landin, P. N., Fritzin, J., Van Moer, W., Isaksson, M. & Alvandpour, A. (2012). Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers. IEEE transactions on microwave theory and techniques, 60(6), 1907-1915
Open this publication in new window or tab >>Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers
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2012 (English)In: IEEE transactions on microwave theory and techniques, ISSN 0018-9480, E-ISSN 1557-9670, Vol. 60, no 6, p. 1907-1915Article in journal (Refereed) Published
Abstract [en]

This paper presents a direct model structure for describing class-D outphasing power amplifiers (PAs) and a method for digitally predistorting these amplifiers. The direct model structure is based on modeling differences in gain and delay, nonlinear interactions between the two paths, and differences in the amplifier behavior. The digital predistortion method is designed to operate only on the input signals phases, to correct for both amplitude and phase mismatches. This eliminates the need for additional voltage supplies to compensate for gain mismatch. less thanbrgreater than less thanbrgreater thanModel and predistortion performance are evaluated on a 32-dBm peak-output-power class-D outphasing PA in CMOS with on-chip transformers. The excitation signal is a 5-MHz downlink WCDMA signal with peak-to-average power ratio of 9.5 dB. Using the proposed digital predistorter, the 5-MHz adjacent channel leakage power ratio (ACLR) was improved by 13.5 dB, from -32.1 to -45.6 dBc. The 10-MHz ACLR was improved by 6.4 dB, from -44.3 to -50.7 dBc, making the amplifier pass the 3GPP ACLR requirements.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2012
Keywords
Behavioral modeling, digital predistortion, LINC, outphasing amplifier, power amplifiers (PAs)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-79098 (URN)10.1109/TMTT.2012.2187532 (DOI)000304859000016 ()
Note
Funding Agencies|Swedish Research Council (VR)||Excellence Center, Linkoping-Lund in Information Technology (ELLIIT)||Research Foundation Flanders (FWO)||Flemish Government (METH1)||LM Ericsson Research Foundation||Ericsson Research||Available from: 2012-06-29 Created: 2012-06-29 Last updated: 2019-09-05
Fritzin, J., Svensson, C. & Alvandpour, A. (2011). A +32dBm 1.85GHz Class-D Outphasing RF PA in 130nm CMOS for WCDMA/LTE. In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC). Paper presented at ESSCIRC (pp. 127-130). IEEE
Open this publication in new window or tab >>A +32dBm 1.85GHz Class-D Outphasing RF PA in 130nm CMOS for WCDMA/LTE
2011 (English)In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), IEEE , 2011, p. 127-130Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +32dBm at 1.85 GHz in a standard 130nm CMOS technology. The PA utilizes four on-chip transformers to combine the outputs of eight Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V 130nm process without excessive device voltage stress. Spectral and modulation requirements were met when a WCDMA and an LTE signal (20 MHz, 16-QAM) were applied to the outphasing PA. At +28.0 dBm channel power for the WCDMA signal, the measured ACLR at 5 MHz and 10 MHz offset were −38.7 dBc and −47.0 dBc, respectively. At +24.9 dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was −34.9 dBc. To the authors' best knowledge, the PA presented in this work has a 3.9 dB higher output power compared to published CMOS Class-D RF PAs.

Place, publisher, year, edition, pages
IEEE, 2011
Series
European Solid-State Circuits Conference, ISSN 1930-8833 ; 2011
Keywords
Outphasing, CMOS, power amplifier
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-71858 (URN)10.1109/ESSCIRC.2011.6044881 (DOI)978-1-4577-0702-5 (ISBN)978-1-4577-0703-2 (ISBN)
Conference
ESSCIRC
Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2019-09-05Bibliographically approved
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