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Backenius, Erik
Publications (10 of 15) Show all publications
Backenius, E., Vesterbacka, M. & Settu, V. (2007). Reduction of simultaneous switching noise in analog signal band. In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07 (pp. 148-151).
Open this publication in new window or tab >>Reduction of simultaneous switching noise in analog signal band
2007 (English)In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07, 2007, p. 148-151Conference paper, Published paper (Refereed)
Abstract [en]

In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.

Keywords
CMOS integrated circuits, adders, flip-flops, frequency-domain analysis, mixed analog-digital integrated circuits, analog signal band, digital clock frequency, frequency components, frequency domain, higher transistor count, pipelined adders, precharged differential cascode switch logic, static CMOS logic, switching noise reduction, transistor level
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14449 (URN)10.1109/ECCTD.2007.4529558 (DOI)978-1-4244-1341-6 (ISBN)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
Backenius, E. (2007). Reduction of Substrate Noise in Mixed-Signal Circuits. (Doctoral dissertation). : Institutionen för systemteknik
Open this publication in new window or tab >>Reduction of Substrate Noise in Mixed-Signal Circuits
2007 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In many consumer products, e.g., cellular phones and handheld computers, both digital and analog circuits are required. Nowadays, it is possible to implement a large subsystem or even a complete system, that earlier required several chips, on a single chip. A system on chip (SoC) has generally the advantages of lower power consumption and a smaller fabrication cost compared with multi-chip solutions. The switching of digital circuits generates noise that is injected into the silicon substrate. This noise is known as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the performance of the circuit. This is a major design issue in mixed-signal ICs where analog and digital circuits share the same substrate.

Two new noise reduction methods are proposed in this thesis work. The first focuses n reducing the switching noise generated in digital clock buffers. The strategy is to use a clock with long rise and fall times in conjunction with a special D flip-flop. It relaxes the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip implemented in a 0.35 μm CMOS technology show that the method can be implemented in an IC with low cost in terms of speed and power consumption. A noise reduction up to 50% is obtained by using the method. The measured power consumption of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers.

The second noise reduction method focuses on reducing simultaneous switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as close to periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. For this purpose we use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 μm CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB using the proposed method. The cost is mainly an increase in power consumption of almost a factor of three.

Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling if no guard band is used, up to a certain frequency that is dependent of the test case. Introducing a guard band resulted in a higher attenuation of substrate noise in bulk than in SOI.

An on-chip measurement circuit aiming at measuring simultaneous switching noise has been designed in a 0.13 μm SOI CMOS technology. The measuring circuit uses a single comparator per channel where several passes are used to capture the waveform. Measurements on a fabricated testchip indicate that the measuring circuit works as intended.

A small part of this thesis work has been done in the area of digit representation in digital circuits. A new approach to convert a number from two’s complement representation to a minimum signed-digit representation is proposed. Previous algorithms are working either from the LSB to the MSB (right-to-left) or from the MSB to the LSB (left-to-right). The novelty in the proposed algorithm is that the conversion is done from left-to-right and right-to-left concurrently. Using the proposed algorithm, the critical path in a conversion circuit can be nearly halved compared with the previous algorithms. The area and power consumption, of the implementation of the proposed algorithm, are somewhere between the left-to-right and right-to-left implementations.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2007
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1094
Keywords
Mixed-signal, Substrate noise, Substrate modeling, Simultaneous switching noise, SSN, Digital, Analog, Clock
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-8813 (URN)978-91-85715-12-1 (ISBN)
Public defence
2007-05-10, Key1, Key-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Note
Articles I, II, III, IV, VII and IX are published with permisson from IEEE dated 07/05/18. Copyright IEEE.Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-04-21
Backenius, E., Säll, E. & Gustafsson, O. (2006). Bidirectional Conversion to Minimum Signed-Digit Representation. In: Circuits and Systems, 2006. ISCAS 2006.: .
Open this publication in new window or tab >>Bidirectional Conversion to Minimum Signed-Digit Representation
2006 (English)In: Circuits and Systems, 2006. ISCAS 2006., 2006Conference paper, Published paper (Other academic)
Abstract [en]

In this work an approach to converting a number in two's complement representation to a minimum signed-digit representation is proposed. The novelty in this work is that this conversion is done from left-to-right and right-to-left concurrently. Hence, the execution time is significantly decreased, while the area overhead is small.

Keywords
Boolean functions, digital arithmetic, bidirectional conversion, signed-digit representation
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14450 (URN)10.1109/ISCAS.2006.1693109 (DOI)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2015-03-11
Backenius, E., Vesterbacka, M. & Hägglund, R. (2006). Effect of simultaneous switching noise on an analog filter. In: Proc. Int. Conf. on Electronics, Circuits and Systems, ICECS'06 (pp. 898-901).
Open this publication in new window or tab >>Effect of simultaneous switching noise on an analog filter
2006 (English)In: Proc. Int. Conf. on Electronics, Circuits and Systems, ICECS'06, 2006, p. 898-901Conference paper, Published paper (Refereed)
Abstract [en]

In this work a digital filter is placed on the same chip as an analog filter. We investigate how the simultaneous switching noise is propagated from the digital filter to different nodes on a manufactured chip. Conventional substrate noise reduction methods are used, e.g., separate power supplies, guard rings, and multiple pins for power supplies. We also investigate if the effect of substrate noise on the analog filter can be reduced by using a noise reduction method, which use long rise and fall times of the digital clock. The measured noise on the output of the analog filter was reduced by 30% up to 50% when the method was used.

Keywords
clocks, digital filters, integrated circuit noise, mixed analog-digital integrated circuits
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14446 (URN)10.1109/ICECS.2006.379934 (DOI)1-4244-0395-2 (ISBN)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
Backenius, E., Säll, E., Andersson, O. & Vesterbacka, M. (2006). Programmable reference generator for on-chip measurement. In: Proc. 24th IEEE Norchip Conf., NORCHIP'06 (pp. 89-92).
Open this publication in new window or tab >>Programmable reference generator for on-chip measurement
2006 (English)In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 89-92Conference paper, Published paper (Refereed)
Abstract [en]

In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

Keywords
comparators, digital-analog conversion, electric noise measurement, integrated circuit measurement, integrated circuit noise, programmable circuits, reference circuits
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14448 (URN)10.1109/NORCHP.2006.329251 (DOI)1-4244-0772-9 (ISBN)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
Backenius, E. & Vesterbacka, M. (2006). Reduction of simultaneous switching noise in digital circuits. In: Proc. 24th IEEE Norchip Conf., NORCHIP'06 (pp. 187-190).
Open this publication in new window or tab >>Reduction of simultaneous switching noise in digital circuits
2006 (English)In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 187-190Conference paper, Published paper (Refereed)
Abstract [en]

In this paper the authors present results from measurements on a test chip used to evaluate our method for reduction of substrate noise that originates from the clock in digital circuits. The authors use long rise and fall times of the clock signal and a D flip-flop that operates well with this clock. With this approach, smaller clock buffers can be used, which results in smaller current peaks on the power supply lines and therefore less switching noise. The measured substrate noise on the test chip was reduced by 20% and up to 54%. With optimized clock buffers this method has a potential of an even larger noise reduction.

Keywords
CMOS integrated circuits, buffer circuits, clocks, flip-flops, integrated circuit noise, integrated circuit testing
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14445 (URN)10.1109/NORCHP.2006.329207 (DOI)1-4244-0772-9 (ISBN)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
Backenius, E. & Vesterbacka, M. (2005). Introduction to substrate noise in SOI CMOS integrated circuits. In: Proc. National Conf. on Radio Science, RVK'05.
Open this publication in new window or tab >>Introduction to substrate noise in SOI CMOS integrated circuits
2005 (English)In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper, Published paper (Other academic)
Abstract [en]

In this paper an introduction to substrate noise in silicon oninsulator (SOI) is given. Differences between substratenoise coupling in conventional bulk CMOS and SOICMOS are discussed and analyzed by simulations. The efficiencyof common substrate noise reduction methods arealso analyzed. Simulation results show that the advantageof the substrate isolation in SOI is only valid up to a frequencythat highly depends on the chip structure. In bulk,guard bands are normally directly connected to the substrate.In SOI, the guard bands are coupled to the substratevia the parasitic capacitance of the silicon oxide. Therefore,the efficiency of a guard may be much larger in aconventional bulk than in SOI. One opportunity in SOI isthat a much higher resistivity of the substrate can be used,which results in a significantly higher impedance up to afrequency where the coupling is dominated by the capacitivecoupling of the substrate.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14447 (URN)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
Backenius, E. (2005). On Reduction of Substrate Noise in Mixed-Signal Circuits. (Licentiate dissertation). : Institutionen för systemteknik
Open this publication in new window or tab >>On Reduction of Substrate Noise in Mixed-Signal Circuits
2005 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach.

In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise.

In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2005. p. 46
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1178
Keywords
mixed-signal, substrate noise, substrate modeling, simultaneous switching noise, SSN, digital, analog, clock
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-6526 (URN)91-85299-78-2 (ISBN)
Presentation
2005-06-17, Visionen, Hus B, Campus US, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Note
Report code: LiU-Tek-Lic-2005:33.Available from: 2006-05-24 Created: 2006-05-24 Last updated: 2009-02-12
Backenius, E. & Vesterbacka, M. (2005). Pin assignment for low simultaneous switching noise. In: Proc. Swedish System-on-Chip Conf., SSoCC'05.
Open this publication in new window or tab >>Pin assignment for low simultaneous switching noise
2005 (English)In: Proc. Swedish System-on-Chip Conf., SSoCC'05, 2005Conference paper, Published paper (Other academic)
Abstract [en]

Simultaneous switching noise (SSN) can degrade the performance of digital circuits. In mixed-signal circuits, the performance of analog circuits are degraded by the SSN that is spread from digital circuits through the substrate to the analog circuits. The most critical parameter when considering SSN is the parasitic inductance in the power supply path from off-chip to on-chip. In this paper, basic theories of inductance of current paths are given for parallel interconnects throughout examples. The results from these examples show that the placement of interconnects plays a big role for the effective inductance. Power supply interconnects should be placed with small distances in between, and so that currents in adjacent interconnects are in opposite directions. With this strategy, a low inductance in the power supply current path can be achieved. The importance of choosing a good package for the silicon die is also briefly discussed.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-37156 (URN)33811 (Local ID)33811 (Archive number)33811 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-14
Backenius, E. & Vesterbacka, M. (2004). A digital circuit with relaxed clocking. In: Proc. Swedish System-on-Chip Conf., SSoCC'04.
Open this publication in new window or tab >>A digital circuit with relaxed clocking
2004 (English)In: Proc. Swedish System-on-Chip Conf., SSoCC'04, 2004Conference paper, Published paper (Other academic)
Abstract [en]

A clock with adjustable rise and fall time is used in conjunction with a D flip-flop that operates well with this clock. Its intended use is to relax the design of the clock network in digital circuits and to alleviate the problems with simultaneous switching noise in mixed-signal circuits. A test chip has been designed in a 0.35 μm CMOS process. The chip consists of a clock driver with adjustable rise and fall times, and an FIR filter that uses the special D flip-flop in the registers. According to measurements, the digital circuit works well when the rise and fall times of the clock is varied from 0.5 ns to 10 ns. This makes the propagation delay in the critical path to vary between 13.0 ns and 13.7 ns, and the energy dissipation to vary between 1.5 pJ and 1.7 pJ, for an input signal with a transition activity of 0.4.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-22876 (URN)2217 (Local ID)2217 (Archive number)2217 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2009-10-14
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