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Caputa, Peter
Publications (10 of 18) Show all publications
Caputa, P. & Svensson, C. (2006). A 3 Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency. In: Proceedings of the International Conference on VLSI Design 2006, Hyderabad, India: (pp. 117-122).
Open this publication in new window or tab >>A 3 Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency
2006 (English)In: Proceedings of the International Conference on VLSI Design 2006, Hyderabad, India, 2006, p. 117-122Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13912 (URN)
Available from: 2006-07-18 Created: 2006-07-18
Caputa, P. & Svensson, C. (2006). An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme. In: International Solid-State Circuits Conference 2006, San Fransisco, USA: .
Open this publication in new window or tab >>An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme
2006 (English)In: International Solid-State Circuits Conference 2006, San Fransisco, USA, 2006Conference paper, Published paper (Other academic)
Abstract [en]

A synchronous latency-insensitive design (SLID) method that mitigates unknown on-chip global wire delays and removes the need for controlling global clock skew is presented. An SLID-based 5.4mm-long on-chip global bus, fabricated in a standard 0.18mum CMOS process, supports 3Gb/s/wire and accepts plusmn2 clock cycles of data-clock skew. This paper focuses on data synchronization for large global on-chip signals, which has become a difficult issue in high-frequency processor designs.

Keywords
CMOS integrated circuits, delays, integrated circuit design, integrated circuit interconnections, synchronisation, 0.18 micron, 5.4 mm, CMOS process, data synchronization, data-clock skew, global clock skew, multicycle communication, on-chip global wire delays, synchronous latency-insensitive design
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13914 (URN)10.1109/ISSCC.2006.1696233 (DOI)1-4244-0079-1 (ISBN)
Available from: 2006-07-18 Created: 2006-07-18
Caputa, P. (2006). Efficient high-speed on-chip global interconnects. (Doctoral dissertation). : Institutionen för systemteknik
Open this publication in new window or tab >>Efficient high-speed on-chip global interconnects
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performancewhile the delay of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. In fact, global interconnects extending across a full chip can have a delay corresponding to multiple clock cycles. At the same time, global clock skew constraints, not only between blocks but also along the pipelined interconnects, become even tighter. On-chip interconnects have always been considered RC-like, that is exhibiting long RC-delays. This has motivated large efforts on alternatives such as on-chip optical interconnects, which have not yet been demonstrated, or complex schemes utilizing on-chip F-transmission or pulsed current-mode signaling.

In this thesis, we show that well-designed electrical global interconnects, behaving as transmission lines, have the capacity of very high data rates (higher than can be delivered by the actual process) and support near velocity-of-light delay for single-ended voltage-mode signaling, thus mitigating the RC-problem. We critically explore key interconnect performance measures such as data delay, maximum data rate, crosstalk, edge rates and power dissipation. To experimentally demonstrate the feasibility and superior properties of on-chip transmission line interconnects, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over the 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 μm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum.

To manage the problems due to global wire delays, we describe and implement a Synchronous Latency Insensitive Design (SLID) scheme, based on source-synchronous data transfer between blocks and data re-timing at the receiving block. The SLIDtechnique not onlymitigates unknown globalwire delays, but also removes the need for controlling global clock skew. The high-performance and high robustness capability of the SLID-method is practically demonstrated through a successful implementation of a SLID-based, 5.4 mm long, on-chip global bus, supporting 3 Gb/s/wire and dynamically accepting ± 2 clock cycles of data-clock skew, in a standard 0.18 μm CMOS porcess.

In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition-energy cost model aimed for efficient power estimation of performancecritical buses. The model, which includes properties that closely capture effects present in high-performance VLSI buses, can be used to more accurately determine the energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a microprocessor cache bus architecture used in industry.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2006
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 992
Keywords
Microelectronics, Global Interconnects, On-Chip Interconnects, Velocity-of-Light Delay, On-Chip Communication, Low-Latency, Transmission Lines
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-7123 (URN)91-85457-87-6 (ISBN)
Public defence
2006-01-27, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2006-07-18 Created: 2006-07-18
Caputa, P. & Svensson, C. (2005). A 3Gb/s/wire, 5mm Long, Low Latency, Global On-Chip Bus in 0.18µm CMOS.. In: SSoCC 2005,2005.
Open this publication in new window or tab >>A 3Gb/s/wire, 5mm Long, Low Latency, Global On-Chip Bus in 0.18µm CMOS.
2005 (English)In: SSoCC 2005,2005, 2005Conference paper, Published paper (Other academic)
Keywords
Interconnect, global interconnect, interconnect delay, on-chip bus, upper-level metal
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-28438 (URN)13578 (Local ID)13578 (Archive number)13578 (OAI)
Note
2 p.Available from: 2009-10-09 Created: 2009-10-09
Källsten, R., Caputa, P. & Svensson, C. (2005). Capacitive Crosstalk Effects on On-Chip Interconnect Latencies and Data-Rates. In: Proceedings of the 23rd Norchip Conference, Oulu, Finland: (pp. 281-284).
Open this publication in new window or tab >>Capacitive Crosstalk Effects on On-Chip Interconnect Latencies and Data-Rates
2005 (English)In: Proceedings of the 23rd Norchip Conference, Oulu, Finland, 2005, p. 281-284Conference paper, Published paper (Other academic)
Abstract [en]

We investigate how crosstalk affects latency, data-rate, and power dissipation for on-chip global interconnects in a 6-layer 0.18μm CMOS process. A simplified analytical interconnect description is compared to circuit simulations of a field solver extracted wire model. We show how repeater insertion can be utilized to achieve wave pipelining, which pushes maximum data-rate beyond the classical limit. Compared to simulations, the analytical model is pessimistic by 10% for latency, 30% for maximum data-rate, and 35% for power dissipation, highlighting the importance of avoiding too simple wire representations.

Keywords
CMOS integrated circuits, circuit simulation, crosstalk, integrated circuit interconnections, integrated circuit modelling, 0.18 micron, CMOS process, capacitive crosstalk effects, circuit simulations, data-rate, on-chip interconnect latencies, power dissipation, wave pipelining
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13913 (URN)10.1109/NORCHP.2005.1597044 (DOI)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-25
Hansson, M., Andersson, S., Caputa, P. & Alvandpour, A. (2005). Laboratory Manual, TSEK01 VLSI Design Project 2006.. Linköping: Bokakademin, LIU
Open this publication in new window or tab >>Laboratory Manual, TSEK01 VLSI Design Project 2006.
2005 (English)Other (Other (popular science, discussion, etc.))
Place, publisher, year, pages
Linköping: Bokakademin, LIU, 2005
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-30383 (URN)15931 (Local ID)15931 (Archive number)15931 (OAI)
Available from: 2009-10-09 Created: 2009-10-09
Caputa, P. & Svensson, C. (2005). Well-Behaved Global On-Chip Interconnect. IEEE Transactions on Circuits and Systems I: Regular Papers, 52(2), 318-323
Open this publication in new window or tab >>Well-Behaved Global On-Chip Interconnect
2005 (English)In: IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1057-7122, Vol. 52, no 2, p. 318-323Article in journal (Refereed) Published
Abstract [en]

Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a scheme to overcome these limitations, based on the utilization of upper-level metals, combined with structured communication architecture. Microwave style transmission lines in upper-level metals allow close-to-velocity-of-light delays if properly dimensioned. As an example, we demonstrate a 480-μm-wide and 20-mm-long bus with a capacity of 320 Gb/s in a nearly standard 0.18-μm process. The process differs from a standard process only through a somewhat thicker outer metal layer. We further illustrate how "self pre-emphasis" at the launch of a data pulse can be used to double the maximum available data rate over a wire. The proposed techniques are scalable, given that higher level metals are properly dimensioned in future processes.

Keywords
interconnect, global interconnect, interconnect delay, on-chip bus, upper-level metal
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13911 (URN)10.1109/TCSI.2004.840483 (DOI)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2010-03-16
Caputa, P., Anders, M. A., Svensson, C., Krishnamurthy, R. K. & Borkar, S. (2004). A Low-swing Single-ended L1 Cache Bus Technique for Sub-90 nm Technologies. In: Proceedings of the European Solid-State Circuits Conference, Leuven, Belgium: (pp. 475-477).
Open this publication in new window or tab >>A Low-swing Single-ended L1 Cache Bus Technique for Sub-90 nm Technologies
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2004 (English)In: Proceedings of the European Solid-State Circuits Conference, Leuven, Belgium, 2004, p. 475-477Conference paper, Published paper (Other academic)
Keywords
global interconnect, low-swing signalling
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13908 (URN)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-07
Caputa, P., Fredriksson, H., Hansson, M., Andersson, S., Alvandpour, A. & Svensson, C. (2004). An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies. In: Proceedings of the Power and Timing Modeling, Optimization and Simulation Conference, Santorini, Greece: (pp. 849-858).
Open this publication in new window or tab >>An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
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2004 (English)In: Proceedings of the Power and Timing Modeling, Optimization and Simulation Conference, Santorini, Greece, 2004, p. 849-858Conference paper, Published paper (Other academic)
Keywords
Transition energy cost model, power estimation, on-chip interconnect
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13909 (URN)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-07
Caputa, P., Fredriksson, H., Hansson, M., Andersson, S., Alvandpour, A. & Svensson, C. (2004). An extended transition energy cost model for buses in deep submicron technologies. In: Enrico Macii, Vassilis Paliouras, Odysseas Koufopavlou (Ed.), Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004. Proceedings (pp. 849-858). Springer Berlin/Heidelberg, 3254
Open this publication in new window or tab >>An extended transition energy cost model for buses in deep submicron technologies
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2004 (English)In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004. Proceedings / [ed] Enrico Macii, Vassilis Paliouras, Odysseas Koufopavlou, Springer Berlin/Heidelberg, 2004, Vol. 3254, p. 849-858Chapter in book (Refereed)
Abstract [en]

In this paper we present and carefully analyze a transition energy cost model aimed for efficient power estimation of performance critical deep submicron buses. We derive an accurate transition energy cost matrix, scalable to buses of arbitrary bit width, which includes properties that closer capture effects present in high-performance VLSI buses. The proposed energy model is verified against Spectre simulations of an implementable bus, including drivers. The average discrepancy between results from Spectre and the suggested model is limited to 4.5% when fringing effects of edge wires is neglected. The proposed energy model can account for effects that limit potential energy savings from bus transition coding.

Place, publisher, year, edition, pages
Springer Berlin/Heidelberg, 2004
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 3254
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-48278 (URN)10.1007/978-3-540-30205-6_87 (DOI)978-3-540-23095-3 (ISBN)978-3-540-30205-6 (ISBN)
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2018-02-12Bibliographically approved
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