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Hansson, Martin
Publications (10 of 29) Show all publications
Fazli Yeknami, A., Hansson, M., Mesgarzadeh, B. & Alvandpour, A. (2010). A low voltage and process variation tolerant SRAM cell in 90-nm CMOS. In:  International Symposium on VLSI Design Automation and Test. Paper presented at VLSI-DAT (pp. 78-81). IEEE.
Open this publication in new window or tab >>A low voltage and process variation tolerant SRAM cell in 90-nm CMOS
2010 (English)In:  International Symposium on VLSI Design Automation and Test, IEEE , 2010, 78-81 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, a new asymmetric 6T (AS6T) SRAM cell is presented in a standard 90-nm CMOS technology employing separate bitline and wordline for read operation. Utilizing separate bitline and wordline during read operation decouples the other cell node from the bitline, hence, enhancing the read static noise margin (SNM) by almost 2 times as compared to the conventional 6T SRAM. The read SNM of 6T and AS6T SRAM cells during a read operation in 1.0 V supply is 85 mV and 159 mV, respectively. The mean μ of the hold SNM for both cells are well above 140 mV, however, the μ of the conventional 6T SRAM is larger than that of AS6T cell. The impact of process parameter variations on read and hold noise margin of the asymmetric 6T cell and the conventional 6T cell, considering various supply voltages, is investigated. The results demonstrate yield improvement, up to 99.5%, and indicate that the supply voltage can scale down to 0.45 V.

Place, publisher, year, edition, pages
IEEE, 2010
Keyword
CMOS memory circuits, SRAM chips, low-power electronics
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-65453 (URN)10.1109/VDAT.2010.5496696 (DOI)978-1-4244-5269-9 (ISBN)
Conference
VLSI-DAT
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2011-02-14
Anders, M., Kaul, H., Hansson, M., Krishnamurthy, R. & Borkar, S. (2008). A 2.9Tb/s 8W 64-Core Circuit-switched Network-on-Chip in 45nm CMOS. In: European Solid-State Circuits Conference,2008 (pp. 182). Bristol: IOP Institute of Physics.
Open this publication in new window or tab >>A 2.9Tb/s 8W 64-Core Circuit-switched Network-on-Chip in 45nm CMOS
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2008 (English)In: European Solid-State Circuits Conference,2008, Bristol: IOP Institute of Physics , 2008, 182- p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Bristol: IOP Institute of Physics, 2008
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-43028 (URN)70939 (Local ID)70939 (Archive number)70939 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Hansson, M. (2008). Low-Power Clocking and Circuit Techniques for Leakage and Process Variation Compensation. (Doctoral dissertation). Linköping: Linköping University Electronic Press.
Open this publication in new window or tab >>Low-Power Clocking and Circuit Techniques for Leakage and Process Variation Compensation
2008 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Over the last four decades the integrated circuit industry has evolved in a tremendous pace. This success has been driven by the scaling of device sizes leading to higher and higher integration capability, which have enabled more functionality and higher performance. The impressive evolution of modern high-performance microprocessors have resulted in chips with over a billion transistors as well as multi-GHz clock frequencies. As the silicon integrated circuit industry moves further into the nanometer regime, scaling of device sizes is still predicted to continue at least into the near future. However, there are a number of challenges to overcome to be able to continue the increase of integration at the same pace. Three of the major challenges are increasing power dissipation due to clocking of synchronous circuit, increasing leakage currents causing growing static power dissipation and reduced circuit robustness, and finally increasing spread in circuit parameters due to physical limitations in the manufacturing process. This thesis presents a number of circuit techniques that aims to help in all three of the mentioned challenges.Power dissipation related to the clock generation and distribution is identified as the dominating contributor of the total active power dissipation for multi-GHz systems. As the complexity and size of synchronous systems continues to increase, clock power will also increase. This makes novel power reduction techniques absolutely crucial in future VLSI design. In this thesis an energy recovering clocking technique aimed at reducing the total chip clock power is presented. Based on theoretical analysis the technique is shown to enable considerable clock power savings. Moreover, the impact of the proposed technique on conventional flip-flop topologies is studied. Measurements on an experimental chip design proves the technique, and shows more than 56% lower clock power compared to conventional clock distribution techniques at clock frequencies up to 1.76 GHz.Static leakage power dissipation is a considerable contributor to the total power dissipation. This power is dissipated even for circuits that are idle and not contributing to the operation. Hence, with increasing number of transistors on each chip, circuit techniques which reduce the static leakage currents are necessary. In this thesis a technique is discussed which reduces the static leakage current in a microcode ROM resulting in 30% reduction of the leakage power with no area or performance penalty.Apart from increasing static power dissipation the increasing leakage currents also impact the robustness constraints of the circuits. This is important for regenerative circuits like flip-flops and latches where a changed state due to leakage will lead to loss of functionality. This is a serious issue especially for high-performance dynamic circuits, which are attractive in order to limit the clock load in the design. However, with the increasing leakage the robustness of dynamic circuits reduces dramatically. To improve the leakage robustness for sub-90 nm low clock load dynamic flip-flops, a novel keeper technique is proposed. The proposed keeper utilizes a scalable and simple leakage compensation technique, which is implemented on a reconfigurable flip-flop. At normal clock frequencies the flip-flop is configured in dynamic mode, and reduces the clock power by 25% due to the lower clock load. During any low-frequency operation, the flip-flop is configured as a static flip-flop retaining full functional robustness.As scaling continues further towards the fundamental atomistic limits, several challenges arise for continuing industrial device integration. Large inaccuracies in lithography process, impurities in manufacturing, and reduced control of dopant levels during implantation all cause increasing statistical spread of performance, power, and robustness of the devices. In order to compensate the impact of the increasingly large process variations on latches and flip-flops, a reconfigurable keeper technique is presented in this thesis. In contrast to the traditional design for worst-case process corners, a variable keeper circuit is utilized. The proposed reconfigurable keeper preserves the robustness of storage nodes across the process corners without degrading the overall chip performance.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2008. 188 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1197
Keyword
Low-power, resonant clocking, multi-GHz, CMOS, leakage tolerance, low-leakage techniques, process variation, process variation compensation
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-12495 (URN)978-91-7393-847-1 (ISBN)
Public defence
2008-08-29, Visionen, B-huset, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2008-09-10 Created: 2008-09-08 Last updated: 2009-04-29Bibliographically approved
Hansson, M. & Alvandpour, A. (2007). Comparative analysis of process variation impact on flip-flop power-performance.. In: IEEE International Symposium on Circuits and Systems,2007 (pp. 3744). Stoughton, USA: The Printing House, Inc..
Open this publication in new window or tab >>Comparative analysis of process variation impact on flip-flop power-performance.
2007 (English)In: IEEE International Symposium on Circuits and Systems,2007, Stoughton, USA: The Printing House, Inc. , 2007, 3744- p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Stoughton, USA: The Printing House, Inc., 2007
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-38366 (URN)43907 (Local ID)43907 (Archive number)43907 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Hansson, M. & Alvandpour, A. (2007). Impact of process variation on flip-flop power-performance in 90nm CMOS.. In: Swedish System-on-Chip Conference SSoCC,2007. Göteborg: CTH.
Open this publication in new window or tab >>Impact of process variation on flip-flop power-performance in 90nm CMOS.
2007 (English)In: Swedish System-on-Chip Conference SSoCC,2007, Göteborg: CTH , 2007Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Göteborg: CTH, 2007
Keyword
flip-flop, CMOS, process-variation, design-margins
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-38037 (URN)41346 (Local ID)41346 (Archive number)41346 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Mesgarzadeh, B., Hansson, M. & Alvandpour, A. (2007). Jitter Characteristic in Charge Recovery Resonant Clock Distribution. IEEE Journal of Solid-State Circuits, 42(7), 1618-1625 .
Open this publication in new window or tab >>Jitter Characteristic in Charge Recovery Resonant Clock Distribution
2007 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 42, no 7, 1618-1625 p.Article in journal (Refereed) Published
Abstract [en]

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

Keyword
CMOS digital integrated circuits, clocks, jitter, resonators
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14898 (URN)10.1109/JSSC.2007.896691 (DOI)
Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2017-12-13
Mesgarzadeh, B., Hansson, M. & Alvandpour, A. (2007). Low-Power Bufferless Resonant Clock Distribution Networks. In: Proceedings of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS): (pp. 960-963). Montreal: ReSMiQ.
Open this publication in new window or tab >>Low-Power Bufferless Resonant Clock Distribution Networks
2007 (English)In: Proceedings of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Montreal: ReSMiQ , 2007, 960-963 p.Conference paper, Published paper (Refereed)
Abstract [en]

The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.

Place, publisher, year, edition, pages
Montreal: ReSMiQ, 2007
Keyword
CMOS integrated circuits, VLSI, clocks, timing jitter
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14900 (URN)10.1109/MWSCAS.2007.4488725 (DOI)
Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2009-05-08
Mesgarzadeh, B., Hansson, M. & Alvandpour, A. (2007). Low-power low-jitter bufferless resonant clocking.. In: Swedish System-on-Chip Conference SSoCC,2007. Göteborg: CTH.
Open this publication in new window or tab >>Low-power low-jitter bufferless resonant clocking.
2007 (English)In: Swedish System-on-Chip Conference SSoCC,2007, Göteborg: CTH , 2007Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Göteborg: CTH, 2007
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-38036 (URN)41345 (Local ID)41345 (Archive number)41345 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-15
Hansson, M., Mesgarzadeh, B. & Alvandpour, A. (2006). 1.56 HGz On-chip Resonant Clocking in 130nm CMOS.. In: IEEE Custom Integrated Circuits Conference CICC,2006 (pp. 241). Piscataway: IEEE.
Open this publication in new window or tab >>1.56 HGz On-chip Resonant Clocking in 130nm CMOS.
2006 (English)In: IEEE Custom Integrated Circuits Conference CICC,2006, Piscataway: IEEE , 2006, 241- p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Piscataway: IEEE, 2006
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-35097 (URN)24848 (Local ID)24848 (Archive number)24848 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-15
Hansson, M., Mesgarzadeh, B. & Alvandpour, A. (2006). 1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS. In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC) (pp. 464-467). .
Open this publication in new window or tab >>1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
2006 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, 464-467 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

Keyword
CMOS digital integrated circuits, clocks, electric noise measurement, integrated circuit noise, jitter
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14044 (URN)10.1109/ESSCIR.2006.307481 (DOI)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2010-01-14Bibliographically approved
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