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Hägglund, Robert
Publications (10 of 20) Show all publications
Hägglund, R. (2006). An optimization-based approach to efficient design of analog circuits. (Doctoral dissertation). Institutionen för systemteknik
Open this publication in new window or tab >>An optimization-based approach to efficient design of analog circuits
2006 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Traditional design methods for analog circuits are based on rules-of-thumbs, experience, and trial-and-error approaches involving the use of circuit simulators. It is an unstructured process, which is time-consuming, error prone, and requires the attention of a skilled analog designer. This situation calls for design methodologies that are more efficient.

We have developed an efficient approach and corresponding tools that address these issues. A computer-aided design tool for design of large analog circuits with low level of human intervention has been developed. The tool combines efficient performance measure evaluation and optimization methods to determine the device sizes and generate layouts for analog circuits. Large analog circuits with about 200 devices have been designed. The circuits are optimized with respect to, e.g., power consumption, and subject to a large number of performance requirements. All performance measures are automatically derived, which reduces the probability of introducing errors.

Experimental results indicate that our approach can be used to design robust highperformance analog circuits with improved performance compared to manual approaches. Furthermore, the computer-aided tool decreases both the overall design time and the time required of a skilled designer.

We have developed a technique that derives the performance equations directly from the circuit schematics as well as techniques for efficient evaluation of the equations. This approach reduces the risk of introducing errors and enables the use of accurate device models, i.e., high-accuracy equations without approximations are obtained.

In fully differential circuits, common-mode stabilization is required. Even though a multitude of common-mode feedback circuits have been presented in the literature, the performance requirements for these circuits are rarely fully explained. Here, the common-mode feedback design problem is addressed to gain design insights. A Volterra series model is used to analyze the distortion terms caused by the use of a common-mode feedback. From this analysis, the DC gain, bandwidth, and stability requirements of the common-mode loop are discussed.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2006. p. 248
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1026
Keywords
Analog circuit design, computer-aided design
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-7477 (URN)91-85523-61-5 (ISBN)
Public defence
2006-06-02, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Available from: 2006-09-28 Created: 2006-09-28 Last updated: 2013-11-25
Backenius, E., Vesterbacka, M. & Hägglund, R. (2006). Effect of simultaneous switching noise on an analog filter. In: Proc. Int. Conf. on Electronics, Circuits and Systems, ICECS'06 (pp. 898-901).
Open this publication in new window or tab >>Effect of simultaneous switching noise on an analog filter
2006 (English)In: Proc. Int. Conf. on Electronics, Circuits and Systems, ICECS'06, 2006, p. 898-901Conference paper, Published paper (Refereed)
Abstract [en]

In this work a digital filter is placed on the same chip as an analog filter. We investigate how the simultaneous switching noise is propagated from the digital filter to different nodes on a manufactured chip. Conventional substrate noise reduction methods are used, e.g., separate power supplies, guard rings, and multiple pins for power supplies. We also investigate if the effect of substrate noise on the analog filter can be reduced by using a noise reduction method, which use long rise and fall times of the digital clock. The measured noise on the output of the analog filter was reduced by 30% up to 50% when the method was used.

Keywords
clocks, digital filters, integrated circuit noise, mixed analog-digital integrated circuits
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14446 (URN)10.1109/ICECS.2006.379934 (DOI)1-4244-0395-2 (ISBN)
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
Hägglund, R., Hjalmarson, E. & Wanhammar, L. (2005). Automated Design of Analog Filters at Transistor Level. In: Swedish System-on-Chip Conferance,2005.
Open this publication in new window or tab >>Automated Design of Analog Filters at Transistor Level
2005 (English)In: Swedish System-on-Chip Conferance,2005, 2005Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34532 (URN)21717 (Local ID)21717 (Archive number)21717 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Hjalmarson, E., Hägglund, R. & Wanhammar, L. (2005). Time and Performance Efficient Design of Analog Circuits. In: Radiovetenskap och Kommunikation,2005 (pp. 181-186).
Open this publication in new window or tab >>Time and Performance Efficient Design of Analog Circuits
2005 (English)In: Radiovetenskap och Kommunikation,2005, 2005, p. 181-186Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34533 (URN)21718 (Local ID)21718 (Archive number)21718 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Hägglund, R., Hjalmarson, E. & Wanhammar, L. (2004). Automated Device Sizing of Analog Circuits With Yield Enhancement. In: Swedish System-on-Chip Conference 2004,2004.
Open this publication in new window or tab >>Automated Device Sizing of Analog Circuits With Yield Enhancement
2004 (English)In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper, Published paper (Other academic)
Keywords
Automated Sizing Analog Circuits
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-23632 (URN)3124 (Local ID)3124 (Archive number)3124 (OAI)
Available from: 2009-10-07 Created: 2009-10-07
Hägglund, R., Hjalmarson, E. & Wanhammar, L. (2004). Yield Enhancement Techniques in Analog Design Automation. In: IEEE NorChip Conf,2004.
Open this publication in new window or tab >>Yield Enhancement Techniques in Analog Design Automation
2004 (English)In: IEEE NorChip Conf,2004, 2004Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-23599 (URN)3089 (Local ID)3089 (Archive number)3089 (OAI)
Available from: 2009-10-07 Created: 2009-10-07
Hjalmarson, E., Hägglund, R. & Wanhammar, L. (2003). A Design Platform for Computer-Aided Design of Analog Amplifiers. In: Swedish System-on-Chip Conferance,2003.
Open this publication in new window or tab >>A Design Platform for Computer-Aided Design of Analog Amplifiers
2003 (English)In: Swedish System-on-Chip Conferance,2003, 2003Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34548 (URN)21776 (Local ID)21776 (Archive number)21776 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Hjalmarson, E., Hägglund, R. & Wanhammar, L. (2003). An Equation-Based Optimization Approach for Analog Circuit Design. In: International Symposium on Signals, Circuits Systems,2003 (pp. 77-80).
Open this publication in new window or tab >>An Equation-Based Optimization Approach for Analog Circuit Design
2003 (English)In: International Symposium on Signals, Circuits Systems,2003, 2003, p. 77-80Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34550 (URN)21778 (Local ID)21778 (Archive number)21778 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Hjalmarson, E., Hägglund, R. & Wanhammar, L. (2003). An Optimization-Based Approach for Analog Circuit Design. In: European Conference on Circuit Theory and Design,2003 (pp. 369-372).
Open this publication in new window or tab >>An Optimization-Based Approach for Analog Circuit Design
2003 (English)In: European Conference on Circuit Theory and Design,2003, 2003, p. 369-372Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34530 (URN)21715 (Local ID)21715 (Archive number)21715 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Hjalmarson, E., Hägglund, R. & Wanhammar, L. (2003). Design space exploration and trade-offs in analog amplifier design. In: Jorge Juan Chico and Enrico Macii (Ed.), Jorge Juan Chico, Enrico Macii (Ed.), Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. Proceedings. Paper presented at 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003 (pp. 338-347). Springer Berlin/Heidelberg, 2799
Open this publication in new window or tab >>Design space exploration and trade-offs in analog amplifier design
2003 (English)In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. Proceedings / [ed] Jorge Juan Chico, Enrico Macii, Springer Berlin/Heidelberg, 2003, Vol. 2799, p. 338-347Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we discuss an optimization-based approach for design space exploration to find limitations and possible trade-offs between performance metrics in analog circuits. The exploration guides the designer when making design decisions. For the design space exploration, which is expensive in terms of computation time, we use an optimization-based device sizing tool that runs concurrent optimization tasks on a network of workstations. The tool enables efficient and accurate exploration of the available design space. As a design example, we investigate three operational transconductance amplifiers, OTAs, implemented in a standard 0.35-mum CMOS process. This example shows that large savings in terms of chip area and power consumption can be made by selecting the most suitable circuit.

Place, publisher, year, edition, pages
Springer Berlin/Heidelberg, 2003
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 2799
National Category
Computer Sciences Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-48493 (URN)10.1007/978-3-540-39762-5_40 (DOI)000186330400040 ()3-540-20074-6 (ISBN)978-3-540-20074-1 (ISBN)978-3-540-39762-5 (ISBN)
Conference
13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2018-02-20Bibliographically approved
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