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Mesgarzadeh, Behzad
Publications (10 of 42) Show all publications
Ojani, A., Mesgarzadeh, B. & Alvandpour, A. (2015). Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 62(1), 273-282
Open this publication in new window or tab >>Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers
2015 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 62, no 1, p. 273-282Article in journal (Refereed) Published
Abstract [en]

Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-110393 (URN)10.1109/TCSI.2014.2347231 (DOI)000347706500029 ()
Available from: 2014-09-10 Created: 2014-09-10 Last updated: 2019-09-05Bibliographically approved
Ojani, A., Mesgarzadeh, B. & Alvandpour, A. (2014). A Low-Power Direct IQ Upconversion Technique Based on Duty-Cycled Multi-Phase Sub-Harmonic Passive Mixers for UWB Transmitters. In: : . Paper presented at The International Symposium on Integrated Circuits (ISIC), December 10-12, Singapore.
Open this publication in new window or tab >>A Low-Power Direct IQ Upconversion Technique Based on Duty-Cycled Multi-Phase Sub-Harmonic Passive Mixers for UWB Transmitters
2014 (English)Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a low-power direct-conversion IQ modulator for ultra-wideband (UWB) communications based on multi-phase duty-cycled sub-harmonic passive mixers. The novelty of the proposed architecture is in employing a quadrature mixer array in such a configuration that the upconvertion of the baseband signal can be performed using a much lower LO frequency, i.e., a sub-harmonic frequency of the carrier. As a result, several benefits can be gained. Requiring a sub-harmonic LO (SHLO) relaxes the requirements on the frequency synthesizer circuitry. Moreover, the need for digital power-hungry or analog inductor-based high frequency LO buffers is alleviated. In addition, since rail-to-rail LO signals can be provided easier and with less power consumption at lower frequencies, we can employ passive mixers in the mixer array to improve the power consumption and linearity of the overall transmitter. Multi-phase LO clocks required by the proposed scheme are provided using a delay-locked loops (DLL). The proposed architecture is utilized in design of a WiMedia-UWB direct-conversion TX in a standard 65-nm CMOS technology. The MC simulation results indicate LO leakage of –68 dBc and sideband rejection of –39 dBc. The overall system draw 6.8 mA from a 1.2 V supply.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-110407 (URN)
Conference
The International Symposium on Integrated Circuits (ISIC), December 10-12, Singapore
Available from: 2014-09-10 Created: 2014-09-10 Last updated: 2019-09-05Bibliographically approved
Ojani, A., Mesgarzadeh, B. & Alvandpour, A. (2014). A Self-Calibration Technique for Fast-Switching Frequency-Hopped UWB Synthesis. In: Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014,: . Paper presented at Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014, June 19-21, Lublin, Poland (pp. 154-159). IEEE
Open this publication in new window or tab >>A Self-Calibration Technique for Fast-Switching Frequency-Hopped UWB Synthesis
2014 (English)In: Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014,, IEEE , 2014, p. 154-159Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a self-calibration technique for a fast-switching DLL-based frequency synthesizer targeting frequency-hopped ultra-wideband (UWB) communication. The proposed architecture employs the concept of track-and-hold (T/H) technique to sample the lock control voltages regarding each channel and store them across a corresponding capacitor during a start-up phase. During the normal operation when the hopping command arrives, the stored voltages are applied to the loop in an open-loop regime to perform fast channel switching of sub-9.5 ns which is required by WiMedia-UWB standard. Certain architectural and circuit methods are utilized in order to minimize the error in the sampled voltages caused by channel charge injection and clock feedthrough of the sampling switches. Since the proposed fast-switching scheme does not require a wide loop bandwidth, the existing tradeoff in phase-locked systems between the settling time and the control voltage ripples resulting in sideband spurs is eliminated. Moreover, the VCDL can be biased in the low-gain region of its transfer function to reduce its noise transfer to the synthesizer output. The proposed architecture is implemented in a 65-nm standard CMOS process and the simulation results indicate a worst-case band switching time of less than 5.5 ns.

Place, publisher, year, edition, pages
IEEE, 2014
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing
Identifiers
urn:nbn:se:liu:diva-110397 (URN)10.1109/MIXDES.2014.6872176 (DOI)000345852100030 ()978-83-63578-03-9 (ISBN)
Conference
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014, June 19-21, Lublin, Poland
Available from: 2014-09-10 Created: 2014-09-10 Last updated: 2019-09-05
Ojani, A., Mesgarzadeh, B. & Alvandpour, A. (2014). Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 61(11), 3075-3084
Open this publication in new window or tab >>Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 11, p. 3075-3084Article in journal (Refereed) Published
Abstract [en]

Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the out-of-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of $-$45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.

Place, publisher, year, edition, pages
IEEE, 2014
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-110392 (URN)10.1109/TCSI.2014.2321188 (DOI)000344467500003 ()
Available from: 2014-09-10 Created: 2014-09-10 Last updated: 2019-09-05
Mesgarzadeh, B. (2014). Simultaneous switching noise reduction by resonant clock distribution networks. Integration, 47(2), 242-249
Open this publication in new window or tab >>Simultaneous switching noise reduction by resonant clock distribution networks
2014 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 47, no 2, p. 242-249Article in journal (Refereed) Published
Abstract [en]

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.

Place, publisher, year, edition, pages
Elsevier, 2014
Keywords
EMI; Resonant clock distribution; Simultaneous switching noise (SSN); Sine-wave clock
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-105233 (URN)10.1016/j.vlsi.2013.10.002 (DOI)000331027800008 ()
Available from: 2014-03-14 Created: 2014-03-14 Last updated: 2017-12-05
Ojani, A., Mesgarzadeh, B. & Alvandpour, A. (2013). A quadrature UWB frequency synthesizer with dynamic settling-time calibration. In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013: . Paper presented at 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013; Beijing; China (pp. 2480-2483). IEEE
Open this publication in new window or tab >>A quadrature UWB frequency synthesizer with dynamic settling-time calibration
2013 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE , 2013, p. 2480-2483Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a quadrature DLL-based architecture for WiMedia ultra-wideband (UWB) frequency synthesis. I and Q carriers are directly generated by combining the quadrature multi-phase outputs of the DLL, using separate edge combiners (EC). A variable-stage voltage-controlled delay line (VCDL) scheme is proposed to provide the corresponding output phases to each EC, without the need for multiplexing the DLL outputs for different bands. Moreover, to prevent possible synthesizer hopping time degradation due to dynamic variations in temperature and voltage, a monitoring mechanism is employed to measure the time error at the instant of band switching, and compensate for it if it is beyond a limited value. The Synthesizer is implemented in a standard 65-nm CMOS technology and the simulation results indicate a hopping time of 4.5 to 8.8 ns across process corners. Simulated phase noise at 1 MHz offset from 4488 MHz carrier is -115 dBc/Hz and the worst case spur suppression is -31 dBc. The synthesizer consumes 13.9 mA from a 1.2-V supply.

Place, publisher, year, edition, pages
IEEE, 2013
Series
Circuits and Systems (ISCAS), ISSN 0271-4302
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-106536 (URN)10.1109/ISCAS.2013.6572382 (DOI)000332006802174 ()978-1-4673-5760-9 (ISBN)
Conference
2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013; Beijing; China
Available from: 2014-05-12 Created: 2014-05-09 Last updated: 2019-09-05Bibliographically approved
Bhide, A., Esmailzadeh Najari, O., Mesgarzadeh, B. & Alvandpour, A. (2013). An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS. IEEE Transactions on Circuits and Systems - II - Express Briefs, 60(7), 387-391
Open this publication in new window or tab >>An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
2013 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 60, no 7, p. 387-391Article in journal (Refereed) Published
Abstract [en]

This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2013
Keywords
Digital Delta Sigma modulator (DDSM), digital-to-analog converter (DAC), MASH, oversampling, time interleaving
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-96713 (URN)10.1109/TCSII.2013.2258272 (DOI)000322030600004 ()
Note

Funding Agencies|Swedish Foundation for Strategic Research (SSF)||

Available from: 2013-08-23 Created: 2013-08-23 Last updated: 2019-09-05
Fritzin, J., Mesgarzadeh, B. & Alvandpour, A. (2012). A Class-D Stage with Harmonic Suppression and DLL-Based Phase Generation. In: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS): . Paper presented at 55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 45-48). Lida Ray Technologies Inc.,
Open this publication in new window or tab >>A Class-D Stage with Harmonic Suppression and DLL-Based Phase Generation
2012 (English)In: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), Lida Ray Technologies Inc., , 2012, p. 45-48Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a Class-D stage with 3rd harmonic suppression operating at 2V(DD) (i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Omega load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.

Place, publisher, year, edition, pages
Lida Ray Technologies Inc.,, 2012
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-96564 (URN)10.1109/MWSCAS.2012.6291953 (DOI)000312667200012 ()978-1-4673-2525-7 (ISBN)978-1-4673-2526-4 (ISBN)
Conference
55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
Available from: 2013-08-21 Created: 2013-08-20 Last updated: 2019-09-05
Fritzin, J., Mesgarzadeh, B. & Alvandpour, A. (2012). A Class-D Stage with Third Harmonic Suppression and DLL-Based Phase Generation. Paper presented at 55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2012), 5-8 August 2012, Boise, Idaho, USA.
Open this publication in new window or tab >>A Class-D Stage with Third Harmonic Suppression and DLL-Based Phase Generation
2012 (English)Conference paper, Published paper (Refereed)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-86343 (URN)
Conference
55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2012), 5-8 August 2012, Boise, Idaho, USA
Available from: 2012-12-13 Created: 2012-12-13 Last updated: 2019-09-05
Ojani, A., Mesgarzadeh, B. & Alvandpour, A. (2012). A DLL-based Injection-Locked Frequency Synthesizer for WiMedia UWB. In: 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012): . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS 2012), 20-23 May 2012, Seoul, Korea (South) (pp. 2027-2030). IEEE
Open this publication in new window or tab >>A DLL-based Injection-Locked Frequency Synthesizer for WiMedia UWB
2012 (English)In: 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), IEEE , 2012, p. 2027-2030Conference paper, Published paper (Refereed)
Abstract [en]

A WiMedia ultrawideband (UWB) frequency synthesizer is designed for band group #1. A very fast hopping is achieved by using a delay-locked loop (DLL) architecture which utilizes a novel variable gain voltage-controlled delay line (VCDL) scheme to compensate the phase error generated at the hopping instant. Fast-settling DLL allows an injection-locked oscillator (ILO) to be employed to reduce the current consumption in the edge combiner (EC). Simulated in STM 65-nm CMOS technology, synthesizer hopping time is less than two reference cycles. Phase noise at 3432 MHz is -124 dBc/Hz at 1 MHz offset. The adjacent spur level from the Monte Carlo simulation is -34 dBc. Excluding CML divider, the synthesizer draws 6.7 mW from a 1.2 V supply.

Place, publisher, year, edition, pages
IEEE, 2012
Series
IEEE International Symposium on Cicuits and Systems, ISSN 0271-4302 ; 2012
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-86342 (URN)10.1109/ISCAS.2012.6271678 (DOI)000316903702060 ()978-1-4673-0218-0 (ISBN)978-1-4673-0219-7 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS 2012), 20-23 May 2012, Seoul, Korea (South)
Available from: 2012-12-13 Created: 2012-12-13 Last updated: 2019-09-05Bibliographically approved
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