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Carlsson, Jonas
Publications (10 of 11) Show all publications
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2006). A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems. In: IEEE NORCHIP,2006.
Open this publication in new window or tab >>A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems
2006 (English)In: IEEE NORCHIP,2006, 2006Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-35029 (URN)24686 (Local ID)24686 (Archive number)24686 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Carlsson, J. (2006). Contributions to Asynchronous Communication Ports for GALS Systems. (Doctoral dissertation). Institutionen för systemteknik
Open this publication in new window or tab >>Contributions to Asynchronous Communication Ports for GALS Systems
2006 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Digital systems commonly use a single global clock signal to synchronize the whole system. This is not always possible and it can be more advantageously to divide the system into separate clock domains, where each clock domain can operate with its own clock frequency. Communication between the different clock domains are not trivial and must be handled with care. Several schemes can be used depending on the relation between the clock frequencies of the communicating clock domains. This thesis focuses on the Globally Asynchronous Locally Synchronous (GALS) scheme, in which all communications between clock domains are handled using dedicated communication channels. These communication channels use asynchronous handshaking protocols to transfer information between clock domains. No global clock signal is used and the clock signal is instead local for each clock domain.

An efficient design flow for GALS system has been developed, which allows a designer to implement GALS systems without prior knowledge of asynchronous circuits. The GALS design flow starts with a high-level model of the system behavior and ends with an implementation in an FPGA or an ASIC. The design flow can also increase the design efficiency for GALS system since the flow alleviates the design and placement of the asynchronous circuits for the designer. A tool that handles the asynchronous circuits in the design flow has been developed.

Two types of communication ports have been developed to handle the communication between clock domains. Both of these ports can be used in systems with static schedule or dynamic schedule of transactions. One of the communication ports can easily be migrated to a new CMOS process, since it only uses standard-cells that care provided by most vendors of CMOS processes. A clock gating circuit has been developed to allow a clock domain to use an external stable clock signal to create an internal stoppable clock signal. A stoppable local clock is used to eliminate problems with metastability when transferring data between clock domains with arbitrary clock frequencies.

In order to validate the design flow and proposed circuitry, has an integrated circuit for 2-dimensional Discrete Cosine Transform been implemented using the GALS scheme and one of the proposed communication ports. The circuit has been implemented using a standard-cell library in a 0.35 mm CMOS process. A few possible improvements to the implementation are also discussed in the thesis.

The GALS design flow with the asynchronous wrapper generation tool has been used to implement the digital baseband processing in the physical layer of the IEEE 802.11a transmitter. The transmitter is built using multiple clock domains. The transmitter has been implemented and tested in a Stratix II FPGA.

Place, publisher, year, edition, pages
Institutionen för systemteknik, 2006. p. 144
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1062
Keywords
GALS, Asynchronous, Asynchronous communication ports, Clock gating, Clock domains
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-8038 (URN)9185643300 (ISBN)
Public defence
2006-12-15, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Available from: 2007-02-01 Created: 2007-02-01 Last updated: 2017-12-15
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2006). Design Flow for Globally Asynchronous Locally Synchronous Systems using Conventional Synchronous Design Tools. WSEAS Transactions on Circuits and Systems, 5(7), 953-960
Open this publication in new window or tab >>Design Flow for Globally Asynchronous Locally Synchronous Systems using Conventional Synchronous Design Tools
2006 (English)In: WSEAS Transactions on Circuits and Systems, ISSN 1109-2734, Vol. 5, no 7, p. 953-960Article in journal (Other academic) Published
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34736 (URN)22974 (Local ID)22974 (Archive number)22974 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-01-11
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2006). Synchronous Design Flow for Globally Asynchronous Locally Synchronous Systems. In: WSEAS Int. Conf. Circuits,2006.
Open this publication in new window or tab >>Synchronous Design Flow for Globally Asynchronous Locally Synchronous Systems
2006 (English)In: WSEAS Int. Conf. Circuits,2006, 2006Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34735 (URN)22973 (Local ID)22973 (Archive number)22973 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2005). GALS port implementation in FPGA. In: National Conf. Radio Science RVK,2005.
Open this publication in new window or tab >>GALS port implementation in FPGA
2005 (English)In: National Conf. Radio Science RVK,2005, 2005Conference paper, Published paper (Refereed)
Keywords
RVK GALS FPGA
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-37333 (URN)34671 (Local ID)34671 (Archive number)34671 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Carlsson, J. (2005). Studies on asynchronous communication ports for GALS systems. (Licentiate dissertation). Linköping: Linköpings universitet
Open this publication in new window or tab >>Studies on asynchronous communication ports for GALS systems
2005 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

Digital systems generally use a global clock signal for the whole system. A System-on-Chip may have to communicate with the environment, using several different data rates that does not fit well to the single global clock frequency. When designing a digital system, it might be beneficial to divide the system into different clock domains where each domain can operate with its own clock frequency.

In this thesis, various clocking schemes are discussed. The synchronous clocking schemes that are discussed are mesochronous, plesiochronous, rational, oversampling and arbitrary clocking schemes.

The thesis focuses on the Globally Asynchronous Locally Synchronous scheme. This scheme transfers information between the different clock domains through dedicated communication channels. These communication channels use asynchronous handshaking protocols to transfer information without the necessity for a clock.

A communication channel consists of a transmitting and receiving port. Two types of communication ports are proposed in the thesis. The communication ports can be used either in a system with a static schedule or dynamic schedule of transactions. One of the ports can easily be implemented in different CMOS processes, since it only uses standard cells that can be found in most existing CMOS processes standard library.

A 2-dimensional Discrete Cosine Transform has been implemented using the GALS scheme and one of the proposed communication ports. The 2-D DCT has been implemented using a standard cell library supplied by AMS fora 0.35 µm CMOS process. A few improvements to the implementation are also discussed in the thesis.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2005. p. 94
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1163
National Category
Computer Engineering
Identifiers
urn:nbn:se:liu:diva-153085 (URN)LiU-Tek-Lic-2005:18 (Local ID)91-85299-44-8 (ISBN)LiU-Tek-Lic-2005:18 (Archive number)LiU-Tek-Lic-2005:18 (OAI)
Presentation
2005-06-02, Visionen, Campus Valla, Linköping, Sweden, 13:15 (English)
Opponent
Available from: 2019-01-07 Created: 2018-11-28 Last updated: 2019-04-09Bibliographically approved
Zhuang, S., Carlsson, J., Li, W., Palmkvist, K. & Wanhammar, L. (2004). GALS based approach to the implementation of the DWT filter bank. In: International Conference on Signal Processing,2004 (pp. 567). Beijing: Publishing House of Electronics Industry
Open this publication in new window or tab >>GALS based approach to the implementation of the DWT filter bank
Show others...
2004 (English)In: International Conference on Signal Processing,2004, Beijing: Publishing House of Electronics Industry , 2004, p. 567-Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we propose a VLSI implementation method for one-dimensional discrete wavelet transform (1D-DWT) filter bank based on the GALS systems approach. An asynchronous wrapper, which includes two data communication ports and a local clock controller, is designed for the asynchronous data communication between the locally synchronous filtering modules in the wavelet filter bank. The detailed design methodology for the GALS architecture of ID-DWT filter bank is presented, and the circuits are validated with VHDL and implemented with standard CMOS technology.

Place, publisher, year, edition, pages
Beijing: Publishing House of Electronics Industry, 2004
Keywords
ICSP '04, CMOS integrated circuits, VLSI, channel bank filters, data communication, discrete wavelet transforms, CMOS technology, DWT filter bank, VHDL, VLSI implementation method, asynchronous data communication, asynchronous wrapper, clock controller
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34567 (URN)21890 (Local ID)21890 (Archive number)21890 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2004). GALS Implementation of a 2-D DCT Processor. In: Swedish System-on-Chip Conference 2004,2004.
Open this publication in new window or tab >>GALS Implementation of a 2-D DCT Processor
2004 (English)In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper, Published paper (Other academic)
Keywords
gals dct
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-23605 (URN)3095 (Local ID)3095 (Archive number)3095 (OAI)
Available from: 2009-10-07 Created: 2009-10-07
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2004). Port controller for GALS with first come first served function. In: TENCON 2004,2004.
Open this publication in new window or tab >>Port controller for GALS with first come first served function
2004 (English)In: TENCON 2004,2004, 2004Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-23594 (URN)3083 (Local ID)3083 (Archive number)3083 (OAI)
Available from: 2009-10-07 Created: 2009-10-07
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2004). Port controllers for a GALS Implementation of a 2-D DCT Processor. In: 10th International Symposium on Integrated Circuits, Devices and Systems,2004.
Open this publication in new window or tab >>Port controllers for a GALS Implementation of a 2-D DCT Processor
2004 (English)In: 10th International Symposium on Integrated Circuits, Devices and Systems,2004, 2004Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-23614 (URN)3104 (Local ID)3104 (Archive number)3104 (OAI)
Available from: 2009-10-07 Created: 2009-10-07
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