liu.seSearch for publications in DiVA
Change search
Link to record
Permanent link

Direct link
BETA
Vesterbacka, Mark
Publications (10 of 116) Show all publications
Andersson, N. & Vesterbacka, M. (2015). Power-efficient time-to-digital converter for all-digital frequency locked loops. In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD): . Paper presented at European Conference on Circuit Theory and Design (ECCTD) (pp. 300-303). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Power-efficient time-to-digital converter for all-digital frequency locked loops
2015 (English)In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 300-303Conference paper, Published paper (Refereed)
Abstract [en]

An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This architecture allows for an area efficient and power efficient implementation. Thetarget application for the TDC is an all-digital frequency-locked loop which is alsooverviewed in the paper. A prototype chip has been implemented in a 65 nm CMOSprocess with an active core area of 75μmˆ120μm. The time resolution is 5.7 ps with apower consumption of 1.85 mW measured at 50 MHz sampling frequency.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112589 (URN)10.1109/ECCTD.2015.7300008 (DOI)000380498200010 ()978-1-4799-9877-7 (ISBN)
Conference
European Conference on Circuit Theory and Design (ECCTD)
Available from: 2014-12-04 Created: 2014-12-04 Last updated: 2016-09-25Bibliographically approved
Touqir Pasha, M. & Vesterbacka, M. (2014). A modified switching scheme for multiplexer based thermometer-to-binary encoders. In: 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland: . Paper presented at NORCHIP 2014. The Nordic Microelectronics event, 32nd Norchip Conference 27-28 October 2014, Tampere, Finland (pp. 1-4). IEEE
Open this publication in new window or tab >>A modified switching scheme for multiplexer based thermometer-to-binary encoders
2014 (English)In: 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland, IEEE , 2014, p. 1-4Conference paper, Oral presentation only (Refereed)
Abstract [en]

A modified switching scheme for thermometer-to-binary encoders used in time-to-digital converters (TDCs) is presented. The proposed scheme enables power savings up to 40% for a 256 bit encoder by taking advantage of the operating nature of the TDCs and by preventing unnecessary switchings to pass through the encoder tree. The efficiency of the proposed scheme is verified for thermometer encoders of different word lengths. It is observed that the power savings increase with the length of the thermometer encoder.

Place, publisher, year, edition, pages
IEEE, 2014
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113278 (URN)10.1109/NORCHIP.2014.7004733 (DOI)978-1-4799-5442-1 (ISBN)
Conference
NORCHIP 2014. The Nordic Microelectronics event, 32nd Norchip Conference 27-28 October 2014, Tampere, Finland
Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-03-26Bibliographically approved
Touqir Pasha, M., Johansson, T. & Vesterbacka, M. (2014). A novel technique to reduce the supply sensitivity of CMOS ring oscillators.
Open this publication in new window or tab >>A novel technique to reduce the supply sensitivity of CMOS ring oscillators
2014 (English)Manuscript (preprint) (Other academic)
Abstract [en]

A technique to abbreviate the supply sensitivity of CMOS ring oscillators is presented. By switching the power source from the noisy power supply to a battery during sensitive zero crossings the noise performance of the ring oscillator is improved. The proposed technique can be used in conjunction with other regulation techniques to enhance the performance of ring oscillators in phase locked loops. The proposed switching circuit using a pseudo differential ring oscillator are designed in a 65 nm CMOS process to demonstrate the viability of the proposed scheme in deep submicron process with reduced voltage headroom. At 2 GHz the outputclock exhibits a jitter of less than 14 ps while subjected to a 500 mV noise tone at 500 MHz.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113280 (URN)
Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2018-09-17
Andersson, N. & Vesterbacka, M. (2014). A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture. IEEE Transactions on Circuits and Systems - II - Express Briefs, 61(10), 773-777
Open this publication in new window or tab >>A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
2014 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 10, p. 773-777Article in journal (Refereed) Published
Abstract [en]

A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2014
Keywords
CMOS; delay latch; time-to-digital converter (TDC); Vernier
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112180 (URN)10.1109/TCSII.2014.2345289 (DOI)000343320500009 ()
Available from: 2014-11-18 Created: 2014-11-18 Last updated: 2017-12-05
Andersson, N., Vesterbacka, M., Gustafsson, O. & Wikner, J. (2014). Steady-state cycles in digital oscillators.
Open this publication in new window or tab >>Steady-state cycles in digital oscillators
2014 (English)Manuscript (preprint) (Other academic)
Abstract [en]

Digital recursive oscillators locked in steady-state can be used to generate sinusoids with high spectral purity. The locking occurs when the oscillator returns to a previously visited state and repeats its sequence. In this work we propose a new search algorithm and two new search strategies to find all steady-states for a given oscillator configuration. The improvement in spurious-free dynamic range is between 7 and 40 dB compared to previously reported results. The algorithm is also able to find oscillator sequences for more frequencies than previously reported work. A key part of the method is the reduction of the search space made possible by a proposed extension of existing theory on recursive oscillators. Specific properties of digital oscillators in a steady-state are also discussed. It is shown that the initial states can be used to individually control the phase, amplitude, spectral purity, and also cycle length of the oscillator output.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112590 (URN)
Available from: 2014-12-04 Created: 2014-12-04 Last updated: 2015-03-11Bibliographically approved
Unnikrishnan, V. & Vesterbacka, M. (2014). Time-Mode Analog-to-Digital Conversion Using Standard Cells. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 61(12), 3348-3357
Open this publication in new window or tab >>Time-Mode Analog-to-Digital Conversion Using Standard Cells
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 12, p. 3348-3357Article in journal (Refereed) Published
Abstract [en]

Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2014
Keywords
ADC; all-digital; analog-to-digital; Gray-counter; linearization; polynomial-fit; standard cell; synthesizable; time-domain; time-mode; VCO-based ADC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113048 (URN)10.1109/TCSI.2014.2340551 (DOI)000345581200004 ()
Available from: 2015-01-09 Created: 2015-01-08 Last updated: 2017-12-05
Asif, S. & Vesterbacka, M. (2012). Performance analysis of radix-4 adders. Integration, 45(2), 111-120
Open this publication in new window or tab >>Performance analysis of radix-4 adders
2012 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 45, no 2, p. 111-120Article in journal (Refereed) Published
Abstract [en]

We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carry-based adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4 circuit is 24% faster than a 2-bit radix-2 ripple carry adder with slightly larger transistor count, whereas the power consumption is almost the same. A second scheme for radix-2 and radix-4 adders that have a reduced number of transistors in the carry path is also investigated. Simulation results also confirm that the radix-4 adder gives better performance as compared to a standard 2-bit CLA. 32-Bit ripple carry, 2-stage carry select, variable size carry select, and carry skip adders are implemented with the different full adders as building blocks. There are POP savings, with one exception, for the 32-bit adders in the range 8-18% and EDP savings in the range 21-53% using radix-4 as compared to radix-2.

Place, publisher, year, edition, pages
Elsevier, 2012
Keywords
CMOS full adder, Radix-4 adder, Power-delay product, Energy-delay product, Carry-based adder
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-76617 (URN)10.1016/j.vlsi.2011.09.004 (DOI)000301767100001 ()
Available from: 2012-04-13 Created: 2012-04-13 Last updated: 2017-12-07
Touqir Pasha, M. & Vesterbacka, M. (2011). Frequency control schemes for single ended ring oscillators. In: 20th European Conference on Circuit Theory and Design (ECCTD), 2011, August 29-31, Linköping, Sweden: . Paper presented at 20th European Conference on Circuit Theory and Design (ECCTD), 2011, August 29-31, Linköping, Sweden (pp. 361-364). IEEE
Open this publication in new window or tab >>Frequency control schemes for single ended ring oscillators
2011 (English)In: 20th European Conference on Circuit Theory and Design (ECCTD), 2011, August 29-31, Linköping, Sweden, IEEE , 2011, p. 361-364Conference paper, Oral presentation only (Refereed)
Abstract [en]

An analysis of frequency control techniques for inverter based ring oscillators is presented. The aim of this study is to aid the circuit designer in architecture selection appropriate for a specific application. A brief discussion on ring oscillators is presented followed by an overview of the various control schemes. The circuits are realized in a 40 nm CMOS technology and simulated using Spectre. Based on simulation results the different control schemes are characterized in terms power consumption, tuning range and noise performance so as to guide the designer about the control scheme selection.

Place, publisher, year, edition, pages
IEEE, 2011
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113279 (URN)10.1109/ECCTD.2011.6043361 (DOI)978-1-4577-0616-5 (ISBN)978-1-4577-0617-2 (ISBN)
Conference
20th European Conference on Circuit Theory and Design (ECCTD), 2011, August 29-31, Linköping, Sweden
Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-01-21Bibliographically approved
Jalili, A., Sayedi, S. M., Wikner, J., Palmkvist, K. & Vesterbacka, M. (2010). Calibration of high-resolution flash ADCS based on histogram test methods. In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on. Paper presented at 2010 IEEE International Conference on Electronics, Circuits, and Systems, 12-15 Dec. 2010, Athens, Greece (pp. 114-117). IEEE
Open this publication in new window or tab >>Calibration of high-resolution flash ADCS based on histogram test methods
Show others...
2010 (English)In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, IEEE , 2010, p. 114-117Conference paper, Published paper (Other academic)
Abstract [en]

In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.

Place, publisher, year, edition, pages
IEEE, 2010
Keywords
RAM;calibration technique;comparator;generator circuit;high-resolution flash analog-to-digital converter;histogram test method;offset estimation;offset trimming;probability density function;triangular signal generation;trimming circuit;uniform distribution;voltage 1 V;word length 10 bit;word length 8 bit;analogue-digital conversion;calibration;comparators (circuits);probability;random-access storage;signal generators;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70623 (URN)10.1109/ICECS.2010.5724467 (DOI)978-1-4244-8155-2 (ISBN)
Conference
2010 IEEE International Conference on Electronics, Circuits, and Systems, 12-15 Dec. 2010, Athens, Greece
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2011-10-13
Jalili, A., Sayedi, S. M., Wikner, J., Andersson, N. & Vesterbacka, M. (2010). Calibration of sigma-delta analog-to-digital converters based on histogram test methods. In: NORCHIP, 2010. Paper presented at NorChip 2010, 28th Norchip Conference, 15 - 16 November 2010, Tampere, Finland (pp. 1-4). IEEE
Open this publication in new window or tab >>Calibration of sigma-delta analog-to-digital converters based on histogram test methods
Show others...
2010 (English)In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which highspeed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied. It is shown that the calibration technique can cope with errors that occur in the feedback digital-to-analog converter (DAC) and the input accumulator. Behavioral-level simulation results show an improvement of in effective number of bits (ENOB) from 6.6 to 11.3. Fairly large offset and gain errors have been introduced which illustrates a robust calibration technique.

Place, publisher, year, edition, pages
IEEE, 2010
Keywords
#x03A3; #x0394; analog-to-digital converters;calibration technique;feedback digital-to-analog converter;histogram test methods;low-resolution flash subADCs;sigma-delta analog-to-digital converters;calibration;feedback;sigma-delta modulation;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70627 (URN)10.1109/NORCHIP.2010.5669459 (DOI)978-1-4244-8972-5 (ISBN)
Conference
NorChip 2010, 28th Norchip Conference, 15 - 16 November 2010, Tampere, Finland
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2011-10-13
Organisations

Search in DiVA

Show all publications