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Gustafsson, O. & Wanhammar, L. (2017). Basic Arithmetic Circuits. In: Pramod Kumar Meher, Thanos Stouraitis (Ed.), Arithmetic Circuits for DSP Applications: . Wiley-IEEE Press.
Open this publication in new window or tab >>Basic Arithmetic Circuits
2017 (English)In: Arithmetic Circuits for DSP Applications / [ed] Pramod Kumar Meher, Thanos Stouraitis, Wiley-IEEE Press , 2017Chapter in book (Other academic)
Place, publisher, year, edition, pages
Wiley-IEEE Press, 2017
National Category
Computer Systems Signal Processing
Identifiers
urn:nbn:se:liu:diva-140663 (URN)978-1-119-20677-4 (ISBN)
Available from: 2017-09-07 Created: 2017-09-07 Last updated: 2017-09-15Bibliographically approved
Garrido Gálvez, M., Källström, P., Kumm, M. & Gustafsson, O. (2016). CORDIC II: A New Improved CORDIC Algorithm. IEEE Transactions on Circuits and Systems - II - Express Briefs, 63(2), 186-190.
Open this publication in new window or tab >>CORDIC II: A New Improved CORDIC Algorithm
2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 2, 186-190 p.Article in journal (Refereed) Published
Abstract [en]

In this brief, we present the CORDIC II algorithm. Like previous CORDIC algorithms, the CORDIC II calculates rotations by breaking down the rotation angle into a series of microrotations. However, the CORDIC II algorithm uses a novel angle set, different from the angles used in previous CORDIC algorithms. The new angle set provides a faster convergence that reduces the number of adders with respect to previous approaches.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2016
Keyword
CORDIC; friend angles; nanorotation; rotation; uniformly scaled redundant (USR) CORDIC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-126139 (URN)10.1109/TCSII.2015.2483422 (DOI)000370533000014 ()
Available from: 2016-03-15 Created: 2016-03-15 Last updated: 2017-11-30
Källström, P. & Gustafsson, O. (2016). Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs. In: 26th International Conference on Field-Programmable Logic and Applications: . Paper presented at 26th International Conference on Field-Programmable Logic and Applications, Lausanne, Switzerland August 29 - September 2, 2016 (pp. 338-341). Lausanne: IEEE.
Open this publication in new window or tab >>Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs
2016 (English)In: 26th International Conference on Field-Programmable Logic and Applications, Lausanne: IEEE , 2016, 338-341 p.Conference paper, Published paper (Refereed)
Abstract [en]

Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. This carry compression was implemented by letting some cells calculate the carry chain in two bits per cell, while some others calculate the summary output bits. In total the proposed design uses no more hardware than the normal adder. The result shows that the proposed adder is faster than a normal adder for word length larger than 64 bits in Virtex-6 FPGAs.

Place, publisher, year, edition, pages
Lausanne: IEEE, 2016
Series
Field Programmable Logic and Applications, International Conference on, ISSN 1946-1488
National Category
Embedded Systems
Identifiers
urn:nbn:se:liu:diva-131088 (URN)10.1109/FPL.2016.7577348 (DOI)000386610400050 ()9782839918442 (ISBN)9781509008513 (ISBN)
Conference
26th International Conference on Field-Programmable Logic and Applications, Lausanne, Switzerland August 29 - September 2, 2016
Available from: 2016-09-09 Created: 2016-09-07 Last updated: 2016-12-06Bibliographically approved
Alam, S. A. & Gustafsson, O. (2016). On the implementation of time-multiplexed frequency-response masking filters. IEEE Transactions on Signal Processing, 64(15), 3933-3944.
Open this publication in new window or tab >>On the implementation of time-multiplexed frequency-response masking filters
2016 (English)In: IEEE Transactions on Signal Processing, ISSN 1053-587X, E-ISSN 1941-0476, Vol. 64, no 15, 3933-3944 p.Article in journal (Refereed) Published
Abstract [en]

The complexity of narrow transition band finite-length impulse response (FIR) filters is high and can be reduced by using frequency-response masking (FRM) techniques. These techniques use a combination of periodic model and, possibly periodic, masking filters. Time-multiplexing is in general beneficial since only rarely does the technology bound maximum obtainable clock frequency and the application determined required sample rate correspond. Therefore, architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of theperiodic filters are introduced in this work.

We show that FRM filters not only reduces the number of multipliers needed, but also have benefits in terms of memory usage. Despite the total amount of samples to be stored is larger for FRM, it results in fewer memory resources needed in FPGAs and more energy efficient memory schemes in ASICs. In total, the power consumption is significantly reduced compared to a single stage implementation. Furthermore, we show that the choice of the interpolation factor which gives the least complexity for the periodic model filter and subsequent masking filter(s) is a function of the time-multiplexing factor, meaning that the minimum number of multipliers not always correspond to the minimum number of multiplications. Both single-port and dual-port memories are considered and the involved trade-off in number of multipliers and memory complexity is illustrated. The results show that for FPGA implementation, the power reduction ranges from 23% to 68% for the considered examples.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016
Keyword
Frequency-response masking, FIR filter, FPGA, ASIC, time-multiplexing, memories
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-124190 (URN)10.1109/TSP.2016.2557298 (DOI)000379699800009 ()
Note

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Available from: 2016-01-21 Created: 2016-01-21 Last updated: 2017-11-30Bibliographically approved
Gustafsson, O. & Johansson, H. (2015). Decimation Filters for High-Speed Delta-Sigma Modulators With Passband Constraints: General Versus CIC-Based FIR Filters. In: 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS): . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 2205-2208). IEEE conference proceedings.
Open this publication in new window or tab >>Decimation Filters for High-Speed Delta-Sigma Modulators With Passband Constraints: General Versus CIC-Based FIR Filters
2015 (English)In: 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE conference proceedings, 2015, 2205-2208 p.Conference paper, Published paper (Refereed)
Abstract [en]

For high-speed delta-sigma modulators the decimation filters are typically polyphase FIR filters as the recursive CIC filters can not be implemented because of the iteration period bound. In addition, the high clock frequency and short input word length make multiple constant multiplication techniques less beneficial. Instead a realistic complexity measure in this setting is the number of non-zero digits of the FIR filter tap coefficients. As there is limited control of the passband approximation error for CIC-based filters these must in most cases be compensated to meet a passband specification. In this work we investigate the complexity of decimation filters meeting CIC-like stopband behavior, but with a well defined passband approximation error. It is found that the general approach can in many cases produce filters with much smaller passband approximation error at a similar complexity.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2015
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-114500 (URN)10.1109/ISCAS.2015.7169119 (DOI)000371471002135 ()978-1-4799-8391-9 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS)
Funder
eLLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications
Available from: 2015-02-24 Created: 2015-02-24 Last updated: 2016-04-07
Johansson, H. & Gustafsson, O. (2015). Filter-Bank Based All-Digital Channelizers and Aggregators for Multi-Standard Video Distribution. In: IEEE International Conference on Digital Signal Processing (DSP), 2015: . Paper presented at IEEE International Conference on Digital Signal Processing (DSP), Singapore, July 21–24, 2015. (pp. 1117-1120). IEEE.
Open this publication in new window or tab >>Filter-Bank Based All-Digital Channelizers and Aggregators for Multi-Standard Video Distribution
2015 (English)In: IEEE International Conference on Digital Signal Processing (DSP), 2015, IEEE , 2015, 1117-1120 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces all-digital flexible channelizersand aggregators for multi-standard video distribution. The overall problem is to aggregate a number of narrow-band subsignals with different bandwidths (6, 7, or 8 MHz) into one composite wide-band signal. In the proposed scheme, this is carried out through a set of analysis filter banks (FBs), that channelize the subsignals into 1/2-MHz subbands, which subsequently are aggregated through one synthesis FB. In this way, full flexibility with a low computational complexity and maintained quality is enabled. The proposed solution offers orders-of-magnitude complexity reductions as compared with a straightforward alternative. Design examples are included that demonstrate the functionality, flexibility, and efficiency.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-123689 (URN)10.1109/ICDSP.2015.7252052 (DOI)000380506600234 ()978-1-4799-8058-1 (ISBN)
Conference
IEEE International Conference on Digital Signal Processing (DSP), Singapore, July 21–24, 2015.
Available from: 2016-01-08 Created: 2016-01-08 Last updated: 2016-11-14Bibliographically approved
Alam, S. A. & Gustafsson, O. (2015). Generalized Division-Free Architecture and Compact Memory Structure for Resampling in Particle Filters. In: 2015 European Conference on Circuit Theory and Design (ECCTD): . Paper presented at European Conference on Circuit Theory and Design (ECCTD) (pp. 416-419). IEEE Press.
Open this publication in new window or tab >>Generalized Division-Free Architecture and Compact Memory Structure for Resampling in Particle Filters
2015 (English)In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE Press, 2015, 416-419 p.Conference paper, Published paper (Refereed)
Abstract [en]

The most challenging step of implementing particle filtering is the resampling step which replicates particles with large weights and discards those with small weights. In this paper, we propose a generic architecture for resampling which uses double multipliers to avoid normalization divisions and make the architecture  equally efficient for non-powers-of-two number of particles. Furthermore, the complexity of resampling is greatly affected by the size of memories used to store weights. We illustrate that by storing the original weights instead of their cumulative sum and calculating them online reduces the total complexity, in terms of area, ranging from 21% to 45%, while giving up to 50% reduction in memory usage.

Place, publisher, year, edition, pages
IEEE Press, 2015
Keyword
Particle filter, Resampling, Division-Free, Multinomial
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122182 (URN)10.1109/ECCTD.2015.7300060 (DOI)000380498200042 ()
Conference
European Conference on Circuit Theory and Design (ECCTD)
Projects
Parallel Architectures for Sampling Based Nonlinear Filters
Funder
ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications, 3.5
Available from: 2015-10-23 Created: 2015-10-23 Last updated: 2016-09-25Bibliographically approved
Ingemarsson, C. & Gustafsson, O. (2015). On fixed-point implementation of symmetric matrix inversion. In: Proceedings of the European Conference on Circuit Theory and Design (ECCTD): . Paper presented at 2015 European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, 24-26 Aug. 2015 (pp. 440-443). Piscataway, NJ, USA: IEEE.
Open this publication in new window or tab >>On fixed-point implementation of symmetric matrix inversion
2015 (English)In: Proceedings of the European Conference on Circuit Theory and Design (ECCTD), Piscataway, NJ, USA: IEEE , 2015, 440-443 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this work we explore the trade-offs between established algorithms for symmetric matrix inversion for fixed-point hardware implementation. Inversion of symmetric positive definite matrices finds applications in many areas, e.g. in MIMO detection and adaptive filtering. We explore computational complexity and show simulation results where numerical properties are analyzed. We show that LDLT decomposition combined with equation system solving are the most promising algorithm for fixed-point hardware implementation. We further show that simply counting the number of operations does not establish a valid comparison between the algorithms as the required word lengths differ significantly.

Place, publisher, year, edition, pages
Piscataway, NJ, USA: IEEE, 2015
Keyword
matrix inversion, fixed point arithmetic, symmetric matrix
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-124357 (URN)10.1109/ECCTD.2015.7300068 (DOI)000380498200050 ()978-1-4799-9877-7 (ISBN)
Conference
2015 European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, 24-26 Aug. 2015
Available from: 2016-01-27 Created: 2016-01-27 Last updated: 2016-09-25Bibliographically approved
Ingemarsson, C. & Gustafsson, O. (2015). On fixed-point implementation of symmetric matrix inversion. In: Proceedings of the European Conference on Circuit Theory and Design (ECCTD): . Paper presented at 2015 European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, 24-26 Aug. 2015 (pp. 1-4). Piscataway, NJ, USA: IEEE.
Open this publication in new window or tab >>On fixed-point implementation of symmetric matrix inversion
2015 (English)In: Proceedings of the European Conference on Circuit Theory and Design (ECCTD), Piscataway, NJ, USA: IEEE , 2015, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this work we explore the trade-offs between established algorithms for symmetric matrix inversion for fixed-point hardware implementation. Inversion of symmetric positive definite matrices finds applications in many areas, e.g. in MIMO detection and adaptive filtering. We explore computational complexity and show simulation results where numerical properties are analyzed. We show that LDLT decomposition combined with equation system solving are the most promising algorithm for fixed-point hardware implementation. We further show that simply counting the number of operations does not establish a valid comparison between the algorithms as the required word lengths differ significantly.

Place, publisher, year, edition, pages
Piscataway, NJ, USA: IEEE, 2015
Keyword
matrix inversion, fixed point arithmetic, symmetric matrix
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-124357 (URN)10.1109/ECCTD.2015.7300068 (DOI)978-1-4799-9877-7 (ISBN)
Conference
2015 European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, 24-26 Aug. 2015
Available from: 2016-01-27 Created: 2016-01-27 Last updated: 2016-02-11Bibliographically approved
Johansson, H. & Gustafsson, O. (2015). On frequency-domain implementation of digital FIR filters. In: IEEE International Conference on Digital Signal Processing (DSP), 2015: . Paper presented at IEEE International Conference on Digital Signal Processing, Singapore, 21-24 July 2015 (pp. 315-318). IEEE.
Open this publication in new window or tab >>On frequency-domain implementation of digital FIR filters
2015 (English)In: IEEE International Conference on Digital Signal Processing (DSP), 2015, IEEE , 2015, 315-318 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper considers frequency-domain implementation of finite-length impulse response filters. In practical fixed-point arithmetic implementations, the overall system corresponds to a time-varying system which can be represented with either a multirate filter bank, and the corresponding distortion and aliasing functions, or a periodic time-varying impulse-response representation or, equivalently, a set of impulse responses and the corresponding frequency responses. The paper provides systematic derivations and analyses of these representations along with design examples. These representations are useful when analyzing the effect of coefficient quantizations as well as the use of shorter DFT lengths than theoretically required.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-124002 (URN)10.1109/ICDSP.2015.7251883 (DOI)000380506600065 ()9781479980581 (ISBN)
Conference
IEEE International Conference on Digital Signal Processing, Singapore, 21-24 July 2015
Available from: 2016-01-18 Created: 2016-01-18 Last updated: 2016-11-14
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0003-3470-3911

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