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Ahmad, Shakeel
Publications (10 of 13) Show all publications
Ahmad, S. & Dabrowski, J. (2019). Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test. Journal of electronic testing, 35(1), 77-85
Open this publication in new window or tab >>Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test
2019 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 35, no 1, p. 77-85Article in journal (Refereed) Published
Abstract [en]

In this paper a built-in-self-test (BiST) aimed at the third and second intercept point (IP3/IP2) characterization of RF receiver is discussed with a focus on a stimulus generator. The generator is designed based on a specialized phase-lock loop (PLL) architecture with two voltage controlled oscillators (VCOs) operating in GHz frequency range. The objective of PLL is to keep the VCOs frequency spacing under control. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the design of VCOs and analog adder. The PLL reference spurs, critical for the IP3 measurement, are avoided by means of a frequency doubling technique. The circuit is designed in 65nm CMOS. A highly linear analog adder with OIP3amp;gt;+15dBm and ring VCOs with phase noise amp;lt; -104 dBc/Hz at 1MHz offset are used to generate the RF stimulus of total power greater than -22dBm. In simulations a performance sufficient for IP3/IP2 test of a typical RF CMOS receiver is demonstrated.

Place, publisher, year, edition, pages
Springer-Verlag New York, 2019
Keywords
BiST; IP3; IP2 test; On-chip test; Phase noise; PLL; Receiver front-end; RF stimulus; Two-tone generator
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-156108 (URN)10.1007/s10836-019-05780-5 (DOI)000461385300006 ()2-s2.0-85061637306 (Scopus ID)
Available from: 2019-04-03 Created: 2019-04-03 Last updated: 2019-07-01Bibliographically approved
Ahmad, S. & Dabrowski, J. (2011). On-Chip Spectral Test for High-Speed ADCs by ΣΔ Technique. In: European Conference on Circuit Theory and Design (ECCTD). Paper presented at 20th European Conference on Circuit Theory and Design, Linköping, 29-31 Aug. 2011 (pp. 661-664). Linköping, Sweden: IEEE conference proceedings
Open this publication in new window or tab >>On-Chip Spectral Test for High-Speed ADCs by ΣΔ Technique
2011 (English)In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 661-664Conference paper, Published paper (Refereed)
Abstract [en]

Application of the ΣΔ modulation technique to the on-chip spectral test for high-speed A/D converters is presented. The harmonic HD2/HD3 and intermodulation IM2/IM3 test is obtained with one-bit ΣΔ sequence stored in a cyclic memory or generated on line, and applied to an ADC under test through a driving buffer and a simple reconstruction filter. To achieve a dynamic range (DR) suitable for high-performance spectral measurements a frequency plan is used taking into account the type of ΣΔ modulation (low-pass and band-pass) including the FFT processing gain. Higher order modulation schemes are avoided to manage the ΣΔ quantization noise without resorting to a more complicated filter. For spectral measurements up to the Nyquist frequency, we propose a dedicated low-pass/band-pass ΣΔ modulation scheme that limits spreading of the low-frequency quantization noise by ADC under test that tends to obstruct the test measurements at high frequencies. Correction technique for NRTZ encoding suitable for ADCs with very high clock frequencies is put in perspective. The presented technique is illustrated by simulation examples of a Nyquist-rate ADC under test.

Place, publisher, year, edition, pages
Linköping, Sweden: IEEE conference proceedings, 2011
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-73026 (URN)10.1109/ECCTD.2011.6043630 (DOI)978-1-4577-0617-2 (ISBN)978-1-4577-0616-5 (ISBN)
Conference
20th European Conference on Circuit Theory and Design, Linköping, 29-31 Aug. 2011
Available from: 2011-12-14 Created: 2011-12-14 Last updated: 2011-12-21
Qazi, F., Sundström, T., Ahmad, S., Wikner, J., Svensson, C. & Dabrowski, J. (2010). A/D Conversion for Software Defined Radio. In: Henrik Sjöland, Lund University (Ed.), Proceedings of the GigaHerz Symposium 2010. Paper presented at GigaHerz Symposium 2010, 2010-03-09, Lund (pp. 36-36).
Open this publication in new window or tab >>A/D Conversion for Software Defined Radio
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2010 (English)In: Proceedings of the GigaHerz Symposium 2010 / [ed] Henrik Sjöland, Lund University, 2010, p. 36-36Conference paper, Published paper (Other academic)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70617 (URN)
Conference
GigaHerz Symposium 2010, 2010-03-09, Lund
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
Qazi, F., Sundström, T., Wikner, J., Ahmad, S., Svensson, C. & Dabrowski, J. (2010). A/D Conversion for Software Defined Radio: Proceedings of GigaHerz Symposium 2010, Lund University, 9-10 March. In: Proceedings of GigaHerz Symposium 2010, Lund University, 9-10 March (pp. 36). Lund: Lund University
Open this publication in new window or tab >>A/D Conversion for Software Defined Radio: Proceedings of GigaHerz Symposium 2010, Lund University, 9-10 March
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2010 (English)In: Proceedings of GigaHerz Symposium 2010, Lund University, 9-10 March, Lund: Lund University , 2010, p. 36-Conference paper, Published paper (Other academic)
Place, publisher, year, edition, pages
Lund: Lund University, 2010
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-54825 (URN)
Available from: 2010-04-15 Created: 2010-04-15 Last updated: 2018-11-08
Ahmad, S. & Dabrowski, J. (2010). Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator. In: Andrzej Pułka and Tomasz Golonek (Ed.), Proceedings of IEEEInternational Conference on Signals and Electronic Systems, (ICSES 10): . Paper presented at International Conference on Signals and Electronic Systems (ICSES), 7-10 Sept, Gliwice, Poland (pp. 393-396). IEEE
Open this publication in new window or tab >>Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator
2010 (English)In: Proceedings of IEEEInternational Conference on Signals and Electronic Systems, (ICSES 10) / [ed] Andrzej Pułka and Tomasz Golonek, IEEE , 2010, p. 393-396Conference paper, Published paper (Refereed)
Abstract [en]

This work presents a cancellation technique of non-linear distortion components of one-bit digital stimulus sequence which is generated in software by a ΣΔ modulator. The stimulus is stored in a cyclic memory and applied to a circuit under test through a driving buffer and a simple lowpass reconstruction filter. The distortion components originate from buffer imperfections which result in a possible asymmetry between rising and falling edges of a NRTZ waveform representing the encoded stimulus. We show that the distortion components can be cancelled by using a simple predistortion technique. In addition an on-chip DC-calibrated ADC can be used to identify the second-order nonlinear products of the driving buffer. This procedure allows for cancellation of all the second-order distortions before the actual test and it can be extended to the third order terms as well.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-61668 (URN)978-1-4244-5307-8 (ISBN)
Conference
International Conference on Signals and Electronic Systems (ICSES), 7-10 Sept, Gliwice, Poland
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2015-09-14Bibliographically approved
Ahmad, S. & Dabrowski, J. (2010). One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test. Journal of electronic testing
Open this publication in new window or tab >>One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test
2010 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727Article in journal (Other academic) Submitted
Place, publisher, year, edition, pages
Springer, 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-61687 (URN)
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2017-12-12Bibliographically approved
Berry, P. & Ahmad, S. (2010). Sport Aviation of the Future. Possible Concepts for Future Sport Aircraft using Differrent Environmental Friendly Propulsion Concepts . In: ICAS 2010. Paper presented at ICAS 2010 (pp. 10).
Open this publication in new window or tab >>Sport Aviation of the Future. Possible Concepts for Future Sport Aircraft using Differrent Environmental Friendly Propulsion Concepts 
2010 (English)In: ICAS 2010, 2010, p. 10-Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-63175 (URN)
Conference
ICAS 2010
Available from: 2010-12-13 Created: 2010-12-13 Last updated: 2018-09-01
Ahmad, S. (2010). Stimuli Generation Techniques for On-Chip Mixed-Signal Test. (Doctoral dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Stimuli Generation Techniques for On-Chip Mixed-Signal Test
2010 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer.

Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author.

Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques.

A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog  adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2010. p. 162
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1350
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-61712 (URN)978-91-7393-288-2 (ISBN)
Public defence
2010-12-02, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15
Opponent
Supervisors
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17Bibliographically approved
Ahmad, S., Azizi, K., Esmaeil Zadeh, I. & Dabrowski, J. (2010). Two-tone PLL for on-chip IP3 test. In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10). Paper presented at Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30-June, Paris, France (pp. 3549-3552). IEEE
Open this publication in new window or tab >>Two-tone PLL for on-chip IP3 test
2010 (English)In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10), IEEE , 2010, p. 3549-3552Conference paper, Published paper (Refereed)
Abstract [en]

This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-61666 (URN)10.1109/ISCAS.2010.5537812 (DOI)978-1-4244-5308-5 (ISBN)
Conference
Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30-June, Paris, France
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17
Ahmad, S., Azizi, K., Esmaeil Zadeh, I. & Dabrowski, J. (2010). Two-Tone PLL for on-Chip IP3 Test. In: Swedish System-on-Chip Conference. Paper presented at SSoCC.
Open this publication in new window or tab >>Two-Tone PLL for on-Chip IP3 Test
2010 (English)In: Swedish System-on-Chip Conference, 2010Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-65484 (URN)
Conference
SSoCC
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2011-02-11
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