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Sadeghifar, Mohammad Reza
Alternative names
Publications (8 of 8) Show all publications
Sadeghifar, M. R., Wikner, J. & Gustafsson, O. (2014). Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter. In: 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS): . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS), 1-5 June, Melbourne, Australia. (pp. 2465-2468). IEEE
Open this publication in new window or tab >>Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter
2014 (English)In: 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2014, p. 2465-2468Conference paper, Published paper (Refereed)
Abstract [en]

An oversampled digital-to-analog converter including digital Sigma Delta modulator and semi-digital FIR filter can be employed in the transmitter of the VDSL2 technology. To select the optimum set of coefficients for the semi-digital FIR filter, an integer optimization problem is formulated in this work, where the model includes the FIR filter magnitude metrics as well as Sigma Delta modulator noise transfer function. The semi-digital FIR filter is optimized with respect to magnitude constraints according to the International Telecommunication Union Power Spectral Density mask for VDSL2 technology and minimizing analog cost as the objective function. Utilizing the semi-digital FIR filter with one bit DACs, high linearity required in high-bandwidth profiles of VDSL2, can be achieved. The resolution of the conventional DACs are limited by the mismatch between DAC unit elements. By utilizing one-bit DACs in semi-digital FIR filter, there will be less degradation caused by mismatch between unit elements. The optimization problem is solved in two conditions; fixed passband gain and variable passband gain. It is shown in this paper that 38% saving in total number of unit elements can be achieved by employing variable passband gain in the optimization problem.

Place, publisher, year, edition, pages
IEEE, 2014
Keywords
Digital-to-analog converter; DAC; oversampled DAC; semi-digital FIR filter; SDFIR filter; digital Sigma Delta modulator; integer optimization
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113793 (URN)10.1109/ISCAS.2014.6865672 (DOI)000346488600616 ()2-s2.0-84907381691 (Scopus ID)978-1-4799-3432-4 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), 1-5 June, Melbourne, Australia.
Available from: 2015-02-02 Created: 2015-01-30 Last updated: 2018-11-08Bibliographically approved
Sadeghifar, M. R. (2014). On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters. (Licentiate dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element.

In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work.

ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement.

Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line.

In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. p. 52
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1708
Keywords
DAC, RFDAC, SDFIR, FIR, semi-digital FIR filter, digital-to-analog converter, D/A converter, data converter, mixed-signal integrated circuits, mixer DAC, IQ modulator, transmitter
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-114274 (URN)10.3384/lic.diva-114274 (DOI)978-91-7519-122-5 (ISBN)
Presentation
2015-02-13, Visionen, Building B, Campus Valla, Linköping University, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2015-02-19 Created: 2015-02-16 Last updated: 2018-11-08Bibliographically approved
Sadeghifar, M. R., Afzal, N. & Wikner, J. (2013). A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO. In: 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS): . Paper presented at 2013 IEEE International Conference on Electronics, Circuits, and Systems, 8-11 December 2013, Abu Dhabi (pp. 641-644). IEEE
Open this publication in new window or tab >>A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO
2013 (English)In: 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), IEEE , 2013, p. 641-644Conference paper, Published paper (Refereed)
Abstract [en]

A digital-to-RF converter (DRFC) architecture for IQ modulator is proposed in this paper. The digital-RF converter utilizes the mixer DAC concept but a discrete-time oscillatory signal is applied to the digital-RF converter instead of a conventional continuous-time LO. The architecture utilizes a low pass Sigma Delta modulator and a semi-digital FIR filter. The digital Sigma Delta modulator provides a single-bit data stream to a current-mode SDFIR filter in each branch of the IQ modulator. The filter taps are realized as weighted one-bit DACs and the filter response attenuates the out-of-band shaped quantization noise generated by the Sigma Delta modulator. To find the semi-digital FIR filter response, an optimization problem is formulated. The magnitude metrics in out-of-band is set as optimization constraint and the total number of unit elements required for the DAC/mixer is set as the objective function. The proposed architecture and the design technique is described in system level and simulation results are presented to support the feasibility of the solution.

Place, publisher, year, edition, pages
IEEE, 2013
Keywords
Digital-to-analog converter; Mixer DAC; RFDAC; semi-digital FIR filter; SDFIR filter; IQ modulator; digital-RF converters
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-109895 (URN)10.1109/ICECS.2013.6815496 (DOI)000339725900166 ()978-1-4799-2452-3 (ISBN)
Conference
2013 IEEE International Conference on Electronics, Circuits, and Systems, 8-11 December 2013, Abu Dhabi
Available from: 2014-08-28 Created: 2014-08-28 Last updated: 2018-11-08Bibliographically approved
Sadeghifar, M. R. & Wikner, J. (2013). Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators. In: ISCAS 2013: . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China (pp. 578-581). IEEE
Open this publication in new window or tab >>Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators
2013 (English)In: ISCAS 2013, IEEE , 2013, p. 578-581Conference paper, Published paper (Refereed)
Abstract [en]

In this work, we present an analytical study of aliasing image spurs problem in digital-RF modulators. The inherent finite image rejection ratio of this types modulators is conceptually discussed. A pulse amplitude modulation (PAM) model of the converter is used in the theoretical discussion. Behavioral level simulation of the digital-RF converter model is included. Finite image rejection is a limiting issue in this architecture, and Digital-IF mixing is used to alleviate the problem which is also reviewed and simulated.

Place, publisher, year, edition, pages
IEEE, 2013
Series
IEEE International Symposium on Circuits and Systems. Proceedings, ISSN 0271-4302
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-100896 (URN)10.1109/ISCAS.2013.6571908 (DOI)000332006800142 ()978-1-4673-5760-9 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
Available from: 2013-11-14 Created: 2013-11-14 Last updated: 2018-11-08Bibliographically approved
Afzal, N., Sadeghifar, R. & Wikner, J. (2011). A study on power consumption of modified noise-shaper architectures for Sigma-Delta DACs. In: Circuit Theory and Design (ECCTD), 2011: . Paper presented at 20th European Conference on Circuit Theory and Design (ECCTD 2011), 29-31 August 2011, Linköping, Sweden (pp. 274-277). IEEE
Open this publication in new window or tab >>A study on power consumption of modified noise-shaper architectures for Sigma-Delta DACs
2011 (English)In: Circuit Theory and Design (ECCTD), 2011, IEEE , 2011, p. 274-277Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work as a composite architecture (CA), shows about 9 dB increase in SNR while maintaining a power-consumption at the same level as that of a so-called hybrid architecture (HA). The power estimation is done for modulators on the RTL level using a standard cell library in a 65-nm technology. The modulators are operated at a sampling frequency of 2 GHz.

Place, publisher, year, edition, pages
IEEE, 2011
Keywords
Composite architecture, DAC Complexity, Hybrid architecture, Modulator's Complexity, Noise Shaper, Sigma-Delta Modulator
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-86542 (URN)10.1109/ECCTD.2011.6043335 (DOI)978-1-4577-0617-2 (ISBN)e-978-1-4577-0616-5 (ISBN)
Conference
20th European Conference on Circuit Theory and Design (ECCTD 2011), 29-31 August 2011, Linköping, Sweden
Available from: 2012-12-18 Created: 2012-12-18 Last updated: 2018-11-08
Sadeghifar, M. R. & Wikner, J. (2010). A higher Nyquist-range DAC employing sinusoidal interpolation. In: NORCHIP, 2010: . Paper presented at NORCHIP, 2010, 28th Norchip Conference, 15 - 16 November 2010, Tampere, Finland (pp. 1-4). IEEE
Open this publication in new window or tab >>A higher Nyquist-range DAC employing sinusoidal interpolation
2010 (English)In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper, Published paper (Other academic)
Abstract [en]

This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.

Place, publisher, year, edition, pages
IEEE, 2010
Keywords
Nyquist range DAC;analog interpolation technique;high speed digital-to-analog converter;linear approximation;oscillating signal;sinusoidal interpolation;time domain analysis;upconversion mixer;approximation theory;digital-analogue conversion;interpolation;mixers (circuits);oscillations;time-domain analysis;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70625 (URN)10.1109/NORCHIP.2010.5669460 (DOI)978-1-4244-8972-5 (ISBN)
Conference
NORCHIP, 2010, 28th Norchip Conference, 15 - 16 November 2010, Tampere, Finland
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
Sadeghifar, M. R. & Wikner, J. (2010). A survey of RF DAC Architectures. In: Proceedings of the Swedish System On Chip Conference, SSOCC 2010: . Paper presented at The 10th Swedish System-on-Chip Conference, SSOCC 2010, May 3-4 2010, Kolmården.
Open this publication in new window or tab >>A survey of RF DAC Architectures
2010 (English)In: Proceedings of the Swedish System On Chip Conference, SSOCC 2010, 2010Conference paper, Published paper (Other academic)
Abstract [en]

A brief overview of different approaches to implement highfrequency,digital-to-analog converters (DACs), sometimes also referredto as radio-frequency DACs (RF DACs) or mixer DACs is given.

Recently, there has been a fairly increased activity within this research field. RF CMOS processes have matured and enables a higher degree of integration with high-speed digital circuits at a more reasonable cost. Also, lately, some new advances have been reported which addresses the architectural-level design issues. These new advances include, for example, the implementation of high-speed, digital sigma-delta modulators to be used with RF DACs to further enable an increase of the output frequency of the DACs.

This work presents a small survey on how RF DACs operate and in some sense how they can be implemented. We outline some different architectures and discuss the pros and cons of those. 

Keywords
Digital-to-analog converters, high-frequency data converters, mixer DACs, RF DACs, Sigma-Delta.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70620 (URN)
Conference
The 10th Swedish System-on-Chip Conference, SSOCC 2010, May 3-4 2010, Kolmården
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
Mesgarzadeh, B., Sadeghifar, M. R., Fredriksson, P., Jansson, C., Niklaus, F. & Alvandpour, A. (2009). A low-noise readout circuit in 0.35-μm CMOS for low-cost uncooled FPA infrared network camera. In: Infrared Technology and Applications XXXV, Proceedings of SPIE - The International Society for Optical Engineering, vol 7298: . Paper presented at The International Society for Optical Engineering, April 13, 2009, Orlando, Florida, USA. SPIE - International Society for Optical Engineering, 7298, Article ID 72982F.
Open this publication in new window or tab >>A low-noise readout circuit in 0.35-μm CMOS for low-cost uncooled FPA infrared network camera
Show others...
2009 (English)In: Infrared Technology and Applications XXXV, Proceedings of SPIE - The International Society for Optical Engineering, vol 7298, SPIE - International Society for Optical Engineering, 2009, Vol. 7298, article id 72982FConference paper, Published paper (Refereed)
Abstract [en]

This paper describes a differential readout circuit technique for uncooled Infrared Focal Plane Arrays (IRFPA) sensors. The differential operation allows an efficient rejection of the common-mode noise during the biasing and readout of the detectors. This has been enabled by utilizing a number of blind and thermally-isolated IR bolometers as reference detectors. In addition, a pixel-wise detector calibration capability has been provided in order to allow efficient error corrections using digital signal processing techniques. The readout circuit for a 64×64 test bolometer-array has been designed in a standard 0.35-μm CMOS process. Circuit simulations show that the analog readout at 60 frames/s consumes 30 mW from a 3.3-V supply and results in a noise equivalent temperature difference (NETD) of 125 mK for f/1 infrared optics.

Place, publisher, year, edition, pages
SPIE - International Society for Optical Engineering, 2009
Series
Proceedings of SPIE, the International Society for Optical Engineering, ISSN 0277-786X ; 7298
Keywords
Bolometer; Focal plane array (FPA); Readout circuit; Uncooled infrared imaging
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-21210 (URN)10.1117/12.819826 (DOI)08-1947-564-5 (ISBN)978-08-1947-564-0 (ISBN)
Conference
The International Society for Optical Engineering, April 13, 2009, Orlando, Florida, USA
Available from: 2009-09-30 Created: 2009-09-30 Last updated: 2019-09-05Bibliographically approved
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