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Palmkvist, Kent
Publications (10 of 30) Show all publications
Jalili, A., Sayedi, S. M., Wikner, J., Palmkvist, K. & Vesterbacka, M. (2010). Calibration of high-resolution flash ADCS based on histogram test methods. In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on. Paper presented at 2010 IEEE International Conference on Electronics, Circuits, and Systems, 12-15 Dec. 2010, Athens, Greece (pp. 114-117). IEEE
Open this publication in new window or tab >>Calibration of high-resolution flash ADCS based on histogram test methods
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2010 (English)In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, IEEE , 2010, p. 114-117Conference paper, Published paper (Other academic)
Abstract [en]

In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.

Place, publisher, year, edition, pages
IEEE, 2010
Keywords
RAM;calibration technique;comparator;generator circuit;high-resolution flash analog-to-digital converter;histogram test method;offset estimation;offset trimming;probability density function;triangular signal generation;trimming circuit;uniform distribution;voltage 1 V;word length 10 bit;word length 8 bit;analogue-digital conversion;calibration;comparators (circuits);probability;random-access storage;signal generators;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70623 (URN)10.1109/ICECS.2010.5724467 (DOI)978-1-4244-8155-2 (ISBN)
Conference
2010 IEEE International Conference on Electronics, Circuits, and Systems, 12-15 Dec. 2010, Athens, Greece
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2006). A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems. In: IEEE NORCHIP,2006.
Open this publication in new window or tab >>A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems
2006 (English)In: IEEE NORCHIP,2006, 2006Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-35029 (URN)24686 (Local ID)24686 (Archive number)24686 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2006). Design Flow for Globally Asynchronous Locally Synchronous Systems using Conventional Synchronous Design Tools. WSEAS Transactions on Circuits and Systems, 5(7), 953-960
Open this publication in new window or tab >>Design Flow for Globally Asynchronous Locally Synchronous Systems using Conventional Synchronous Design Tools
2006 (English)In: WSEAS Transactions on Circuits and Systems, ISSN 1109-2734, Vol. 5, no 7, p. 953-960Article in journal (Other academic) Published
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34736 (URN)22974 (Local ID)22974 (Archive number)22974 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-01-11
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2006). Synchronous Design Flow for Globally Asynchronous Locally Synchronous Systems. In: WSEAS Int. Conf. Circuits,2006.
Open this publication in new window or tab >>Synchronous Design Flow for Globally Asynchronous Locally Synchronous Systems
2006 (English)In: WSEAS Int. Conf. Circuits,2006, 2006Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34735 (URN)22973 (Local ID)22973 (Archive number)22973 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2005). GALS port implementation in FPGA. In: National Conf. Radio Science RVK,2005.
Open this publication in new window or tab >>GALS port implementation in FPGA
2005 (English)In: National Conf. Radio Science RVK,2005, 2005Conference paper, Published paper (Refereed)
Keywords
RVK GALS FPGA
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-37333 (URN)34671 (Local ID)34671 (Archive number)34671 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Zhuang, S., Carlsson, J., Li, W., Palmkvist, K. & Wanhammar, L. (2004). GALS based approach to the implementation of the DWT filter bank. In: International Conference on Signal Processing,2004 (pp. 567). Beijing: Publishing House of Electronics Industry
Open this publication in new window or tab >>GALS based approach to the implementation of the DWT filter bank
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2004 (English)In: International Conference on Signal Processing,2004, Beijing: Publishing House of Electronics Industry , 2004, p. 567-Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we propose a VLSI implementation method for one-dimensional discrete wavelet transform (1D-DWT) filter bank based on the GALS systems approach. An asynchronous wrapper, which includes two data communication ports and a local clock controller, is designed for the asynchronous data communication between the locally synchronous filtering modules in the wavelet filter bank. The detailed design methodology for the GALS architecture of ID-DWT filter bank is presented, and the circuits are validated with VHDL and implemented with standard CMOS technology.

Place, publisher, year, edition, pages
Beijing: Publishing House of Electronics Industry, 2004
Keywords
ICSP '04, CMOS integrated circuits, VLSI, channel bank filters, data communication, discrete wavelet transforms, CMOS technology, DWT filter bank, VHDL, VLSI implementation method, asynchronous data communication, asynchronous wrapper, clock controller
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34567 (URN)21890 (Local ID)21890 (Archive number)21890 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2004). GALS Implementation of a 2-D DCT Processor. In: Swedish System-on-Chip Conference 2004,2004.
Open this publication in new window or tab >>GALS Implementation of a 2-D DCT Processor
2004 (English)In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper, Published paper (Other academic)
Keywords
gals dct
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-23605 (URN)3095 (Local ID)3095 (Archive number)3095 (OAI)
Available from: 2009-10-07 Created: 2009-10-07
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2004). Port controller for GALS with first come first served function. In: TENCON 2004,2004.
Open this publication in new window or tab >>Port controller for GALS with first come first served function
2004 (English)In: TENCON 2004,2004, 2004Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-23594 (URN)3083 (Local ID)3083 (Archive number)3083 (OAI)
Available from: 2009-10-07 Created: 2009-10-07
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2004). Port controllers for a GALS Implementation of a 2-D DCT Processor. In: 10th International Symposium on Integrated Circuits, Devices and Systems,2004.
Open this publication in new window or tab >>Port controllers for a GALS Implementation of a 2-D DCT Processor
2004 (English)In: 10th International Symposium on Integrated Circuits, Devices and Systems,2004, 2004Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-23614 (URN)3104 (Local ID)3104 (Archive number)3104 (OAI)
Available from: 2009-10-07 Created: 2009-10-07
Carlsson, J., Palmkvist, K. & Wanhammar, L. (2003). An 8-by-8 Point 2D DCT Processor Based on the GALS Approach. In: IEEE NorChip Conf.,2003.
Open this publication in new window or tab >>An 8-by-8 Point 2D DCT Processor Based on the GALS Approach
2003 (English)In: IEEE NorChip Conf.,2003, 2003Conference paper, Published paper (Refereed)
Keywords
DCT GALS
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-37335 (URN)34674 (Local ID)34674 (Archive number)34674 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
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