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Hammarberg, Jerker
Publications (4 of 4) Show all publications
Hammarberg, J. & Nadjm-Tehrani, S. (2005). Formal verification of fault tolerance in safety-critical reconfigurable modules. International Journal on Software Tools for Technology Transfer (STTT), 7(3), 268-279
Open this publication in new window or tab >>Formal verification of fault tolerance in safety-critical reconfigurable modules
2005 (English)In: International Journal on Software Tools for Technology Transfer (STTT), ISSN 1385-4879, E-ISSN 1571-8115, Vol. 7, no 3, p. 268-279Article in journal (Refereed) Published
Abstract [en]

Demands for higher flexibility in aerospace applications has led to increasing deployment of reconfiguarble modules. In several cases the industry is looking into Field Programmable Gate Arrays (FPGA) as a means of efficient adaption of existing components. This paper addresses the safety analysis issues for reconfigurable modules with an emphasis on FPGAs. FPGAs act as digital hardware but in the context of safety analysis they should be treated as software, i.e. with added demands on formal analysis. The contributions of this paper are twofold. First, we illustrate a development process using a language with formal semantics (Esterel) for design, formal verification of high-level design, and automatic code generation down to synthesizable VHDL. We argue that this process reduces the likelihood of systematic (permanent) faults in the design, and still produces VHDL code that may be of acceptable quality (size of FPGA, delay). Secondly, in a general approach that is equally applicable to other formal design languages, we illustrate how the effect of transient fault modes and faults in external modules can be formally studied. We modularly extended the component design model with fault models that represent specific or random faults (e.g. radiation leading to bit flips in the component under design), and transient or permanent faults in the rest of the environment. Some faults corrupt inputs to the component and others jeopardise the effect of output signals that control the environment. This process supports a formal version of Failure Modes and Effects Analysis (FMEA). The set-up is then used to formally determine which (single or multiple) fault modes cause violation of the top-level safety-related property, much in the spirit of fault-tree analyses (FTA). All of this is done with out building the fault tree and using a common model for design and for safety analyses. An aerospace hydraulic monitoring system is used to illustrate the analysis of fault tolerance. © Springer-Verlag 2004.

Keywords
Esterel, Fault tolerance, Formal verification, FPGA, Safety analysis
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-45440 (URN)10.1007/s10009-004-0152-y (DOI)
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2018-08-14
Hammarberg, J. & Nadjm-Tehrani, S. (2003). Development of Safety-Critical reconfigurable Hardware with Esterel. In: International Workshop on Formal Methods for Industrial Critical Systems FMICS,2003.
Open this publication in new window or tab >>Development of Safety-Critical reconfigurable Hardware with Esterel
2003 (English)In: International Workshop on Formal Methods for Industrial Critical Systems FMICS,2003, 2003Conference paper, Published paper (Refereed)
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-22141 (URN)1249 (Local ID)1249 (Archive number)1249 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-08-14
Hammarberg, J. & Nadjm-Tehrani, S. (2003). Development of Safety-Critical Reconfigurable Hardware with Esterel. In: Proceedings of the 8th Internation Workshop on Formal Methods for Industrial Critical Systems (FMICS'03). Elsevier Publishers
Open this publication in new window or tab >>Development of Safety-Critical Reconfigurable Hardware with Esterel
2003 (English)In: Proceedings of the 8th Internation Workshop on Formal Methods for Industrial Critical Systems (FMICS'03), Elsevier Publishers , 2003Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Elsevier Publishers, 2003
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-61653 (URN)
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2018-08-14
Hammarberg, J. & Nadjm-Tehrani, S. (2003). Development of safety-critical reconfigurable hardware with esterel. Electronical Notes in Theoretical Computer Science, 80
Open this publication in new window or tab >>Development of safety-critical reconfigurable hardware with esterel
2003 (English)In: Electronical Notes in Theoretical Computer Science, ISSN 1571-0661, E-ISSN 1571-0661, Vol. 80, p. 229-244Conference paper, Published paper (Other academic)
Abstract [en]

Demands for higher flexibility in aerospace applications has led to increasing deployment of FPGAs. Clearly, analysis of safety-related properties of such components is essential for their use in safety-critical subsystems. The contributions of this paper are twofold. First, we illustrate a development process, using a language with formal semantics (Esterel) for design, formal verification of high-level design and automatic code generation down to VHDL. We argue that this process reduces the likelihood of systematic (permanent) faults in the design, and still produces VHDL code that is of acceptable quality (size of FPGA, delay). Secondly, we show how the design model can be modularly extended with fault models that represent random faults (e.g. radiation) leading to bit flips in the component under design (resembling FMEA), and transient or permanent faults in the rest of the environment (corrupting inputs to the component or jeopardising the effect of output signals that control the environment). The set-up is then used to formally determine which (single or multiple) fault modes cause violation of the top-level safety-related property, much in the spirit of fault-tree analyses. An aerospace hydraulic monitoring system is used to illustrate the results. © 2003 Published by Elsevier Science B.V.

Keywords
Esterel, Formal Verification, FPGA, Safety Analysis
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-46527 (URN)10.1016/S1571-0661(04)80820-X (DOI)
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2018-08-14
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