liu.seSearch for publications in DiVA
Change search
Link to record
Permanent link

Direct link
BETA
Edman, Anders
Publications (5 of 5) Show all publications
Edman, A., Svensson, C. & Mesgarzadeh, B. (2005). Synchronous Latency-Insensitive Design for Multiple Clock Domain. In: Proceedings of the IEEE International System-on-Chip Conference (SoCC): (pp. 83-86). : IEEE Explore
Open this publication in new window or tab >>Synchronous Latency-Insensitive Design for Multiple Clock Domain
2005 (English)In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), IEEE Explore , 2005, p. 83-86Conference paper, Published paper (Refereed)
Abstract [en]

Modern system-on-chip designs often require multiple clock frequencies. On the other hand, global interconnects suffer large delays. This paper proposes a method that manages these two problems within the framework of conventional synchronous design flow. The design is partitioned into isochronous blocks already at behavioral level, where each block is synchronous using a local clock. The local clock frequencies are assumed related by rational numbers. Communication between blocks is managed with FIFOs at each receiver, which manage different clock frequencies and hide unknown delays or clock skews. This method guarantees clock true implementation of a clock true behavioral description utilizing a predefined block-to-block latency.

Place, publisher, year, edition, pages
IEEE Explore, 2005
Keywords
clocks, integrated circuit design, integrated circuit interconnections, system-on-chip
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14906 (URN)10.1109/SOCC.2005.1554462 (DOI)
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2009-02-17Bibliographically approved
Olausson, M., Edman, A. & Liu, D. (2004). Bit memory instructions for a general CPU. In: 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004.Proceedings.: . Paper presented at The 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04). Banff, Alberta, Canada. July 19-21 2004. (pp. 215-218).
Open this publication in new window or tab >>Bit memory instructions for a general CPU
2004 (English)In: 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004.Proceedings., 2004, p. 215-218Conference paper, Published paper (Refereed)
Abstract [en]

Embedded memories in an application specific integrated circuit (ASIC) consume most of the chip area. Data variables of different widths require more memory than needed because they are rounded up to nearest power of 2, i.e., 6 to 8 bits, 11 to 16 bits, and 25 to 32 bits. This can be avoided by adding two bit oriented load and store instructions. The memories can still be 8, 16 or 32 bits wide, but the loads and stores can have arbitrary variable sizes. The hardware changes within the processor are small and an extra hardware block between the processor and the memory is added.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-102009 (URN)10.1109/IWSOC.2004.1319881 (DOI)0-7695-2182-7 (ISBN)
Conference
The 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04). Banff, Alberta, Canada. July 19-21 2004.
Available from: 2013-11-26 Created: 2013-11-26 Last updated: 2013-11-26
Edman, A. & Svensson, C. (2004). Timing closure through a globally synchronous, timing partitioned design methodology.. In: DAC,2004 (pp. 71). New York: ACM, Inc.
Open this publication in new window or tab >>Timing closure through a globally synchronous, timing partitioned design methodology.
2004 (English)In: DAC,2004, New York: ACM, Inc. , 2004, p. 71-Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
New York: ACM, Inc., 2004
Keywords
timing closure, wire delays, clock skew
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22516 (URN)1775 (Local ID)1775 (Archive number)1775 (OAI)
Available from: 2009-10-07 Created: 2009-10-07
Edman, A., Christensen, J., Emrich, A. & Svensson, C. (2001). A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6um CMOS.. IEEE Journal of Solid-State Circuits, 36, 258-265
Open this publication in new window or tab >>A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6um CMOS.
2001 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 36, p. 258-265Article in journal (Refereed) Published
Abstract [en]

The autocorrelation spectrometer is an important instrument for radio astronomy. In satellite-based spectrometers, low power consumption is essential. The correlator chip presented in this paper reduces the power consumption more than five times compared to other full-custom designs. This has been achieved by reducing the number of clocked transistors, using a compact layout of cells, which reduces wire lengths, and using parallel processing of data. Also, the low power performance is combined with a large number of lags and a high data throughput. The correlator performs 0.5-TMAC operations in 416 lags at a sample rate of 1.28-GSample/s with an input data precision of 1.5-b and a correlation period of one second. The chip is also designed to reduce noise generation by using multiple internal clock phases.

Keywords
clock distribution, CMOS digital integrated circuits, correlators, digital signal processing, integrated circuit design
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34948 (URN)24242 (Local ID)24242 (Archive number)24242 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2017-12-13
Edman, A., Björklid, A. & Söderquist, I. (1998). A 0.8 μm CMOS 350 MHz quadrature direct digital frequency synthesizer with integrated D/A converters. In: 1998 Symposium on VLSI Circuits, 1998. Digest of Technical Papers. Paper presented at 1998 Symposium on VLSI circuits, Honolulu, Hawaii, June 11-13 1998 (pp. 54-55).
Open this publication in new window or tab >>A 0.8 μm CMOS 350 MHz quadrature direct digital frequency synthesizer with integrated D/A converters
1998 (English)In: 1998 Symposium on VLSI Circuits, 1998. Digest of Technical Papers, 1998, p. 54-55Conference paper, Published paper (Refereed)
Abstract [en]

This quadrature DDFS calculates sine and cosine values with a tuning resolution below 1 Hz, by only using an 8 word ROM and interpolation. Two internal 8-bit differential D/A converters generate the four-phase analog output signal. A spurious free dynamic range of 50 dB for low frequencies and 30 dB near Nyquist is achieved.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-88624 (URN)10.1109/VLSIC.1998.688001 (DOI)0-7803-4766-8 (ISBN)
Conference
1998 Symposium on VLSI circuits, Honolulu, Hawaii, June 11-13 1998
Available from: 2013-02-13 Created: 2013-02-13 Last updated: 2013-02-13
Organisations

Search in DiVA

Show all publications