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Mohamed, Abdil
Publications (8 of 8) Show all publications
Mohamed, A., Peng, Z. & Eles, P. I. (2005). A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead. Journal of Computer Science and Technology, 20(2), 216-223
Open this publication in new window or tab >>A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead
2005 (English)In: Journal of Computer Science and Technology, ISSN 1000-9000, E-ISSN 1860-4749, Vol. 20, no 2, p. 216-223Article in journal (Refereed) Published
Abstract [en]

This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.

Keyword
testing, build-in-self test, BIST, wiring-aware, optimization
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-29357 (URN)10.1007/s11390-005-0216-9 (DOI)14680 (Local ID)14680 (Archive number)14680 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2018-01-13
Mohamed, A. (2005). High-Level Techniques for Built-In Self-Test Resources Optimization. (Licentiate dissertation). Linköping: Linköpings universitet
Open this publication in new window or tab >>High-Level Techniques for Built-In Self-Test Resources Optimization
2005 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

Design modifications to improve testability usually introduce large area overhead and performance degradation. One way to reduce the negative impact associated with improved testability is to take testability as one of the constraints during high- level design phases so that systems are not only optimized for area and performance, but also from the testability point of view. This thesis deals with the problem of optimizing testing-hardware resources by taking into account testability constraints at high-levels of abstraction during the design process. Firstly, we have provided an approach to solve the problem of optimizing built-in selftest (BIST) resources at the behavioral and register-transfer levels under testability and testing time constraints. Testing problem identification and BIST enhancement during the optimization process are assisted by symbolic testability analysis. Further, concurrent test sessions are generated, while signature analysis registers sharing conflicts as well as controllability and observability constraints are considered. Secondly, we have introduced the problem of BIST resources insertion and optimization while taking wiring area into account. Testability improvement transformations have been defined and deployed in a hardware overhead minimization technique used during a BIST synthesis process. The technique is guided by the results of symbolic testability analysis and inserts a minimal amount of BIST resources into the design to make it fully testable. It takes into consideration both BIST components cost and wiring overhead. Two design space exploration approaches have been proposed: a simulated annealing based algorithm and a greedy heuristic. Experimental results show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored. The greedy heuristic uses our behavioral and register-transfer levels BIST enhancement metrics to guide BIST synthesis in such a way that the number of testability improvement transformations performed on the design is reduced.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2005. p. 115
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1156
Keyword
testing, system-on-chip, testability, built-in self-test, BIST, wiring-aware
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-28510 (URN)13659 (Local ID)91-85297-90-9 (ISBN)13659 (Archive number)13659 (OAI)
Presentation
(English)
Supervisors
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2018-01-13Bibliographically approved
Mohamed, A., Peng, Z. & Eles, P. I. (2004). A Heuristic for Wiring-Aware Built-In Self-Test Synthesis. In: EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools,2004: . Paper presented at EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, DSD 2004 (pp. 408). Rennes, France: IEEE Computer Society Press
Open this publication in new window or tab >>A Heuristic for Wiring-Aware Built-In Self-Test Synthesis
2004 (English)In: EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools,2004, Rennes, France: IEEE Computer Society Press , 2004, p. 408-Conference paper, Published paper (Refereed)
Abstract [en]

This paper addresses the problem of BIST synthesis that takes into account wiring area. A technique for minimizing BIST hardware overhead is presented. The technique uses results of symbolic testability analysis to guarantee testability of all modules in the design. New behavioral-level BIST enhancement metrics are used to guide synthesis in such a way that the number of testability enhancements is minimized. The technique is not only fast but also adds low BIST overhead.

Place, publisher, year, edition, pages
Rennes, France: IEEE Computer Society Press, 2004
Keyword
BIST, wiring overhead, symbolic testability analysis, testing
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-23201 (URN)10.1109/DSD.2004.1333304 (DOI)2612 (Local ID)0-7695-2203-3 (ISBN)2612 (Archive number)2612 (OAI)
Conference
EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, DSD 2004
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
Mohamed, A., Peng, Z. & Eles, P. I. (2004). A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead. In: The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004,2004: . Paper presented at The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004 (pp. 413-415).
Open this publication in new window or tab >>A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead
2004 (English)In: The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004,2004, 2004, p. 413-415Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes a built-in self-test hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It considers both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.

Keyword
BIST, design for testability, wiring overhead, testing
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-23293 (URN)10.1109/DELTA.2004.10073 (DOI)2719 (Local ID)0-7695-2081-2 (ISBN)2719 (Archive number)2719 (OAI)
Conference
The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
Mohamed, A., Peng, Z. & Eles, P. I. (2003). A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead. In: 4th Workshop on RTL and High Level Testing (WRTLT'03).
Open this publication in new window or tab >>A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead
2003 (English)Other (Other (popular science, discussion, etc.))
Abstract [en]

This paper describes a built-in self-test hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system tomake it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored. Keywords: BIST insertion, test synthesis, wiring area, and Simulated Annealing.

Keyword
testing, BIST, wiring-aware
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-23403 (URN)2845 (Local ID)2845 (Archive number)2845 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
Mohamed, A., Peng, Z. & Eles, P. I. (2002). BIST Synthesis: An Approach to Resources Optimization under Test Time Constraints. In: 5th Design and Diagnostic of Electronic Computer Systems DDECS2002,2002 (pp. 346-351).
Open this publication in new window or tab >>BIST Synthesis: An Approach to Resources Optimization under Test Time Constraints
2002 (English)In: 5th Design and Diagnostic of Electronic Computer Systems DDECS2002,2002, 2002, p. 346-351Conference paper, Published paper (Refereed)
Abstract [en]

An Approach at optimizing the BIST resource usage under test-time constraints is introduced. The test problem identification and BIST enhancement strategy during the optimization process are assisted by symbolic testability analysis. Further, concurrent test sessions are generated, while MISRs sharing conflicts as well as controllability and observability constraints are considered.

Keyword
BIST, resource usage optimization, testability analysis
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-23364 (URN)2800 (Local ID)2800 (Archive number)2800 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
Eles, P. I., Jervan, G., Mohamed, A. & Peng, Z. (2002). Report on Early DfT Support. Linköping, Sweden: Linköpings universitet
Open this publication in new window or tab >>Report on Early DfT Support
2002 (English)Report (Other academic)
Abstract [en]

The main goal of workpackage 3 of the COTEST project was assessment of the feasibility and evaluation of test-oriented system modifications. This report introduces some possible techniques and discuss their effectiveness for early DfT support.

Place, publisher, year, edition, pages
Linköping, Sweden: Linköpings universitet, 2002
Series
COTEST Project Report ; D3
Keyword
design for testability, testing
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-23356 (URN)2791 (Local ID)2791 (Archive number)2791 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
Mohamed, A., Peng, Z. & Eles, P. I. (2001). BIST Synthesis: An Approach to Resource Optimization under Test Time Constraints. Santa Barbara, USA: International Test Synthesis Workshop
Open this publication in new window or tab >>BIST Synthesis: An Approach to Resource Optimization under Test Time Constraints
2001 (English)Other (Other (popular science, discussion, etc.))
Abstract [en]

This paper describes an approach to optimize BIST resource usage for system on chip under testing time constraints. A symbolic testability analysis technique is used to analyze testability of the design for pseudorandom BIST. The testability analysis results are used to guide high-level synthesis of system on chip blocks with BIST mechanisms. Finally, BIST resources are optimized to comply with test time constraints. Key words: BIST, testing time, symbolic testability analysis, and high-level BIST synthesis.

Place, publisher, year, pages
Santa Barbara, USA: International Test Synthesis Workshop, 2001
Keyword
testing, BIST, wiring-aware
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-23401 (URN)2843 (Local ID)2843 (Archive number)2843 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13
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