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Nordqvist, Ulf
Publications (10 of 17) Show all publications
Nordqvist, U. (2004). Protocol processing in network terminals. (Doctoral dissertation). Linköping: Linköpings universitet
Open this publication in new window or tab >>Protocol processing in network terminals
2004 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures dedicated for processing of packets and network protocols.

In the emerging research area of protocol processing, there exist many hardware platform proposals. Most of them aim for router applications, not so many for terminals. As a starting point for terminal research this thesis explores a number of different router design alternatives and some common computer architecture concepts. These concepts and architectures have been examined and evaluated to see if some ideas apply also to protocol processing in network terminals.

Requirements on protocol processors for terminals can be summarized as:

• Low silicon area

• Low power consumption

• Low processing latency

• High processing throughput

• Flexible implementation

Fulfilling these requirements while supporting offtoading of as much protocol processing as possible to the network interface is the key issue of this thesis. Off-loading means that the protocol processing can be executed in a special unit that does not need to execute the host applications as well. The protocol processor unit basically acts as a smart network interface card.

A novel terminal platform solution is proposed in this thesis. The dual processor platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, which operate in parallel, to accelerate the platform in a configurable way. These hardware blocks have been selected and specified to fulfill requirements set by a number of common network protocols. To find these requirements, the protocol processing procedure has been investigated and divided into processing tasks. These different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in the other part of the platform which is a general purpose micro controller.

The dedicated datapath, simplified control, and minimal usage of data buffers make the proposed processor attractive from a power perspective. Further it accelerates the platform so that high speed operation is enabled. Different implementation alternatives are provided in this thesis. Which one to select depends on what kind of terminal the platform is going to be used for. Further this thesis includes a discussion around how the ability to reassembly fragmented packets demands architectural modifications.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2004. p. 162
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 865
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-24075 (URN)3636 (Local ID)91-7373-914-6 (ISBN)3636 (Archive number)3636 (OAI)
Public defence
2004-04-23, Sal Visionen, Linköpings Universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-01-31
Nordqvist, U. (2003). A Programmable Network Interface Accelerator. (Licentiate dissertation). Linköping: Uniserv
Open this publication in new window or tab >>A Programmable Network Interface Accelerator
2003 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures.

In the emerging research area of programmable network interfaces, there exist many hardware platform proposals. Most of them aim for router applications but not so many for terminals. This thesis explores a number of different router design alternatives and architectural concepts. The concepts have been examined to see which apply also to terminal designs.

A novel terminal platform solution is proposed in this thesis. The platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, that operates in parallel, to accelerate the platform. The hardware blocks have been selected and specified to fulfill the requirements set by a number of common network protocols. To do this, the protocol processing procedure has been investigated and divided into processing tasks. The different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in other parts of the platform.

The dedicated datapath, simplified control, and minimal usage of data buffers makes the proposed processor attractive from a power perspective. Further it accelerates the platform so that high speed operation is enabled.

Place, publisher, year, edition, pages
Linköping: Uniserv, 2003. p. 63
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 998
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33282 (URN)19282 (Local ID)91-7373-580-9 (ISBN)19282 (Archive number)19282 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15
Nordqvist, U. & Liu, D. (2003). Control path in a protocol processor. In: Midwest symposium on circuits and systems MWCAS,2003.
Open this publication in new window or tab >>Control path in a protocol processor
2003 (English)In: Midwest symposium on circuits and systems MWCAS,2003, 2003Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-32802 (URN)18734 (Local ID)18734 (Archive number)18734 (OAI)
Available from: 2009-10-09 Created: 2009-10-09
Nordqvist, U. & Liu, D. (2003). Packet Classification and Termination in a Protocol Processor. In: : . Paper presented at Ninth International Symposium on High Performance Computer Architecture. Anaheim, California, February 8-12, 2003. (pp. 88).
Open this publication in new window or tab >>Packet Classification and Termination in a Protocol Processor
2003 (English)Conference paper, Published paper (Other academic)
Abstract [en]

This paper introduces a novel architecture for acceleration of control memory access in a protocol processor dedicated for packet reception in network terminals. The architecture ena'bles the protocol processor to perform high performance reassembly and also offtoads other parts of the control flow processing. The architecture includes packet classification engines and concepts used in modem high-speed routers. The protocol processor combined with a general purpose micro controller, fully offload up to layer 4 processing in multi gigabit networks when implemented in mature standard cell processes.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33275 (URN)19275 (Local ID)19275 (Archive number)19275 (OAI)
Conference
Ninth International Symposium on High Performance Computer Architecture. Anaheim, California, February 8-12, 2003.
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15
Nordqvist, U. & Liu, D. (2003). Packet classification and termination in a protocol processor (1ed.). In: Mark A. Franklin, Patrick Crowley , Haldun Hadimioglu, Peter Z. Onufryk (Ed.), Network processor design - Issues and practices, vol 2: (pp. 159-180). Elsevier
Open this publication in new window or tab >>Packet classification and termination in a protocol processor
2003 (English)In: Network processor design - Issues and practices, vol 2 / [ed] Mark A. Franklin, Patrick Crowley , Haldun Hadimioglu, Peter Z. Onufryk, Elsevier , 2003, 1, p. 159-180Chapter in book (Other academic)
Abstract [en]

Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service. ·Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linköpings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington.·Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.

Place, publisher, year, edition, pages
Elsevier, 2003 Edition: 1
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-32800 (URN)18732 (Local ID)0-12-198157-6 (ISBN)978-0-1219-8157-0 (ISBN)18732 (Archive number)18732 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-18Bibliographically approved
Nordqvist, U. (2003). Power Efficient Packer Buffering in a Protocol Processor. In: Swedish System-onChip Conference,2003.
Open this publication in new window or tab >>Power Efficient Packer Buffering in a Protocol Processor
2003 (English)In: Swedish System-onChip Conference,2003, 2003Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33266 (URN)19265 (Local ID)19265 (Archive number)19265 (OAI)
Available from: 2009-10-09 Created: 2009-10-09
Nordqvist, U. & Liu, D. (2003). Power optimized packet buffering in a protocol processor. In: International conference on electronic circuits and systems, ICECS,2003.
Open this publication in new window or tab >>Power optimized packet buffering in a protocol processor
2003 (English)In: International conference on electronic circuits and systems, ICECS,2003, 2003Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-32803 (URN)18735 (Local ID)18735 (Archive number)18735 (OAI)
Available from: 2009-10-09 Created: 2009-10-09
Nordqvist, U. & Liu, D. (2002). A Comparative Study of Protocol Processors. In: Conference on Computer Science and Systems Engineering,2002 (pp. 107).
Open this publication in new window or tab >>A Comparative Study of Protocol Processors
2002 (English)In: Conference on Computer Science and Systems Engineering,2002, 2002, p. 107-Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33544 (URN)19569 (Local ID)19569 (Archive number)19569 (OAI)
Available from: 2009-10-09 Created: 2009-10-09
Nordqvist, U., Henriksson, T. & Liu, D. (2002). Configurable CRC Generator. In: Design and Diagnostics of Electronics, Circuits and Systems,2002 (pp. 192).
Open this publication in new window or tab >>Configurable CRC Generator
2002 (English)In: Design and Diagnostics of Electronics, Circuits and Systems,2002, 2002, p. 192-Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33599 (URN)19633 (Local ID)19633 (Archive number)19633 (OAI)
Available from: 2009-10-09 Created: 2009-10-09
Henriksson, T., Nordqvist, U. & Liu, D. (2002). Embedded Protocol Processor for Fast and Efficient Packet Reception. In: International Conference on Computer Design,2002 (pp. 414).
Open this publication in new window or tab >>Embedded Protocol Processor for Fast and Efficient Packet Reception
2002 (English)In: International Conference on Computer Design,2002, 2002, p. 414-Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33549 (URN)19574 (Local ID)19574 (Archive number)19574 (OAI)
Available from: 2009-10-09 Created: 2009-10-09
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