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Li, Weidong
Publications (4 of 4) Show all publications
Li, W. & Wanhammar, L. (2004). An offset prefix adder for conversion and addition. In: Swedish System-on-Chip Conference 2004,2004.
Open this publication in new window or tab >>An offset prefix adder for conversion and addition
2004 (English)In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper, Published paper (Other academic)
Keywords
SSoCC´04
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34395 (URN)21403 (Local ID)21403 (Archive number)21403 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Zhuang, S., Carlsson, J., Li, W., Palmkvist, K. & Wanhammar, L. (2004). GALS based approach to the implementation of the DWT filter bank. In: International Conference on Signal Processing,2004 (pp. 567). Beijing: Publishing House of Electronics Industry
Open this publication in new window or tab >>GALS based approach to the implementation of the DWT filter bank
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2004 (English)In: International Conference on Signal Processing,2004, Beijing: Publishing House of Electronics Industry , 2004, p. 567-Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we propose a VLSI implementation method for one-dimensional discrete wavelet transform (1D-DWT) filter bank based on the GALS systems approach. An asynchronous wrapper, which includes two data communication ports and a local clock controller, is designed for the asynchronous data communication between the locally synchronous filtering modules in the wavelet filter bank. The detailed design methodology for the GALS architecture of ID-DWT filter bank is presented, and the circuits are validated with VHDL and implemented with standard CMOS technology.

Place, publisher, year, edition, pages
Beijing: Publishing House of Electronics Industry, 2004
Keywords
ICSP '04, CMOS integrated circuits, VLSI, channel bank filters, data communication, discrete wavelet transforms, CMOS technology, DWT filter bank, VHDL, VLSI implementation method, asynchronous data communication, asynchronous wrapper, clock controller
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34567 (URN)21890 (Local ID)21890 (Archive number)21890 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Ohlsson, H., Li, W., Capello, D. & Wanhammar, L. (2003). Design and implementation of an SRAM layout generator. In: IEEE Norchip Conference,2003 (pp. 216). Denmark: TechnoData A/S
Open this publication in new window or tab >>Design and implementation of an SRAM layout generator
2003 (English)In: IEEE Norchip Conference,2003, Denmark: TechnoData A/S , 2003, p. 216-Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Denmark: TechnoData A/S, 2003
Keywords
NORCHIP '03
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34568 (URN)21893 (Local ID)21893 (Archive number)21893 (OAI)
Available from: 2009-10-10 Created: 2009-10-10
Li, W. (2003). Studies on implementation of low power FFT processors. (Licentiate dissertation). Linköping: Linköpings universitet
Open this publication in new window or tab >>Studies on implementation of low power FFT processors
2003 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

In the last decade, the interest for high speed wireless and on cable communication has increased. Orthogonal Frequency Division Multiplexing (OFDM) is a strong candidates and has been suggested or standardized in those communication systems. One key component in OFDM-based systems is FFT processor, which performs the efficient modulation/demodulation.

There are many FFT architectures. Among them, the pipeline architectures are suitable for the real-time communication systems. This thesis presents the implementation of pipeline FFT processors that has low power consumptions.

We select the meet-in-the-middle design methodology for the implementation of FFT processors. A resource analysis for the pipeline architectures is presented. This resource analysis determines the number of memories, butterflies, and complex multipliers to meet the specification.

We present a wordlengths optimization method for the pipeline architectures. We show that the high radix butterfly can be efficiently implemented with carry-save technique, which reduce the hardware complexity and the delay. We present also an efficient implementation of complex multiplier using distributed arithmetic (DA). The implementation of low voltage memories is also discussed.

Finally, we present a 16-point butterfly using constant multipliers that reduces the total number of complex multiplications. The FFT processor using the 16-point butterflies is a competitive candidate for low power applications.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2003. p. 108
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1030
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-152950 (URN)LiU-TeK-Lic-2003:29 (Local ID)9173736929 (ISBN)LiU-TeK-Lic-2003:29 (Archive number)LiU-TeK-Lic-2003:29 (OAI)
Available from: 2019-03-11 Created: 2019-03-11 Last updated: 2019-04-25Bibliographically approved
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