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Rosén, Jakob
Publications (7 of 7) Show all publications
Zhirkov, I., Petruhins, A. & Rosén, J. (2015). Effect of cathode composition and nitrogen pressure on macroparticle generation and type of arc discharge in a DC arc source with Ti-Al compound cathodes. Surface & Coatings Technology, 281, 20-26
Open this publication in new window or tab >>Effect of cathode composition and nitrogen pressure on macroparticle generation and type of arc discharge in a DC arc source with Ti-Al compound cathodes
2015 (English)In: Surface & Coatings Technology, ISSN 0257-8972, E-ISSN 1879-3347, Vol. 281, p. 20-26Article in journal (Refereed) Published
Abstract [en]

Thin films deposited with unfiltered DC arc plasma from Ti, Ti0.75Al0.25, Ti0.50Al0.50, Ti0.30Al0.70, and Al cathodes were characterized with a scanning electron microscope for quantification of extent of macroparticle incorporation. Depositions were performed in N-2 atmosphere in the pressure range from 10(-6) Torr up to 3 . 10(-2) Torr, and the formation of cathode surface nitride contamination was identified from X-ray diffraction analysis. Visual observation and photographic fixation of the arc spot behavior was simultaneously performed. A reduction in macroparticle generation with decreasing Al content and increasing N-2 pressure was demonstrated. A correlated transformation of the arc from type 2 to the type 1 was visually detected and found to be a function of N-2 pressure and at of Al in the cathode. For the Ti cathode, no arc transformation was detected. These observations can be explained by a comparatively high electrical resistivity and high melting point of Al rich surface nitrides, promoting an arc transformation and a reduction in macropartide generation. (C) 2015 Elsevier B.V. All rights reserved.

Place, publisher, year, edition, pages
ELSEVIER SCIENCE SA, 2015
Keywords
Cathodic arc; Type 1; Compound cathode; Macroparticles; Arc transformation; Cathode poisoning
National Category
Physical Sciences Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-123803 (URN)10.1016/j.surfcoat.2015.09.030 (DOI)000366072200003 ()
Note

Funding Agencies|European Research Council under the European Communitys Seventh Framework Program (FP7)/ERC [258509]; Swedish Research Council (VR) [642-2013-8020]; KAW Fellowship Program

Available from: 2016-01-11 Created: 2016-01-11 Last updated: 2018-01-10
Rosén, J., Neikter, C.-F., Eles, P., Peng, Z., Burgio, P. & Benini, L. (2011). Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip. In: 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'11), Chicago, IL, USA, April 11-14, 2011.: . Paper presented at RTAS11.
Open this publication in new window or tab >>Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip
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2011 (English)In: 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'11), Chicago, IL, USA, April 11-14, 2011., 2011Conference paper, Published paper (Refereed)
Abstract [en]

Optimization techniques for improving the average-case execution time of an application, for which predictability with respect to time is not required, have been investigated for a long time in many different contexts. However, this has traditionally been done without paying attention to the worst-case execution time. For predictable real-time applications, on the other hand, the focus has been solely on worst-case execution time optimization, ignoring how this affects the execution time in the average case. In this paper, we show that having a good average-case delay can be important also for real-time applications for which predictability is required. Furthermore, for real-time applications running on multiprocessor systems-on-chip, we present a technique for optimizing the average case and the worst case simultaneously, allowing for a good average-case execution time while still keeping the worst case as small as possible.

Series
Proceedings of the Real Time and Embedded Technology and Applications Symposium, ISSN 1080-1812
National Category
Information Systems
Identifiers
urn:nbn:se:liu:diva-63779 (URN)10.1109/RTAS.2011.35 (DOI)978-1-61284-326-1 (ISBN)
Conference
RTAS11
Available from: 2011-01-03 Created: 2011-01-03 Last updated: 2018-01-12Bibliographically approved
Rosén, J. (2011). Predictable Real-Time Applications on Multiprocessor Systems-on-Chip. (Licentiate dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Predictable Real-Time Applications on Multiprocessor Systems-on-Chip
2011 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

Being predictable with respect to time is, by definition, a fundamental requirement for any real-time system. Modern multiprocessor systems impose a challenge in this context, due to resource sharing conflicts causing memory transfers to become unpredictable. In this thesis, we present a framework for achieving predictability for real-time applications running on multiprocessor system-on-chip platforms. Using a TDMA bus, worst-case execution time analysis and scheduling are done simultaneously. Since the worst-case execution times are directly dependent on the bus schedule, bus access design is of special importance. Therefore, we provide an efficient algorithm for generating bus schedules, resulting in a minimized worst-case global delay.

We also present a new approach considering the average-case execution time in a predictable context. Optimization techniques for improving the average-case execution time of tasks, for which predictability with respect to time is not required, have been investigated for a long time in many different contexts. However, this has traditionally been done without paying attention to the worst-case execution time. For predictable real-time applications, on the other hand, the focus has been solely on worst-case execution time optimization, ignoring how this affects the execution time in the average case. In this thesis, we show that having a good average-case global delay can be important also for real-time applications, for which predictability is required. Furthermore, for real-time applications running on multiprocessor systems-on-chip, we present a technique for optimizing for the average case and the worst case simultaneously, allowing for a good average case execution time while still keeping the worst case as small as possible. The proposed solutions in this thesis have been validated by extensive experiments. The results demonstrate the efficiency and importance of the presented techniques.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2011. p. 80
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1503
Keywords
Computer Systems, Embedded Systems, Real-Time Systems, Predictability, Multiprocessor Systems
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-70138 (URN)978-91-7393-090-1 (ISBN)
Presentation
2011-09-30, John von Neumann, hus B, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2011-09-12 Created: 2011-08-21 Last updated: 2020-02-03Bibliographically approved
Rosén, J., Eles, P., Peng, Z. & Andrei, A. (2011). Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip. In: 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011.: . Paper presented at DELTA 2011.
Open this publication in new window or tab >>Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip
2011 (English)In: 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011., 2011Conference paper, Published paper (Refereed)
Abstract [en]

Worst-case execution time analysis is the fundament of real-time system design, and is therefore an area which has been subject to great scientific interest for a long time. However, traditional worst-case execution time analysis techniques assume that the underlying hardware is a monoprocessor system, and this class of hardware platforms is getting less suitable for modern embedded applications, which demand more and more in terms of computational power. For multiprocessor systems, traditional worst-case analysis tools do not produce correct results and can consequently not be used. To solve this problem, we have previously proposed a technique for achieving predictability on multiprocessor systems-on-chip using a shared TDMA bus. One of the main benefits with our approach is that existing, traditional worstcase execution time analysis techniques can, after some small modifications, be applied. In this paper, we describe the nature of these modifications and how to handle different types of multiprocessor architectures.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-63323 (URN)10.1109/DELTA.2011.27 (DOI)978-1-4244-9357-9 (ISBN)
Conference
DELTA 2011
Available from: 2010-12-15 Created: 2010-12-15 Last updated: 2017-02-14Bibliographically approved
Rosén, J., Andrei, A., Eles, P. I. & Peng, Z. (2010). Predictable Multiprocessor Systems. In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed).
Open this publication in new window or tab >>Predictable Multiprocessor Systems
2010 (English)In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-59637 (URN)
Available from: 2010-09-22 Created: 2010-09-22 Last updated: 2010-09-27
Andrei, A., Eles, P. I., Peng, Z. & Rosén, J. (2008). Predictable Implementation of Real-Time Applications on Multiprocessor Systems on Chip. In: VLSI Design, 2008. VLSID 2008: . Paper presented at 21st International Conference on VLSI Design (VLSID 2008), 4-8 January 2008, Hyderabad, India (pp. 103-110). IEEE Computer Society
Open this publication in new window or tab >>Predictable Implementation of Real-Time Applications on Multiprocessor Systems on Chip
2008 (English)In: VLSI Design, 2008. VLSID 2008, IEEE Computer Society, 2008, p. 103-110Conference paper, Published paper (Refereed)
Abstract [en]

Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restrictive and particular contexts. One important aspect that makes the analysis difficult is the estimation of the system-s communication behavior. The traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. As opposed to the analysis performed for a single processor system, where the cache miss penalty is constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks- WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this context, we propose, for the first time, an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures.

Place, publisher, year, edition, pages
IEEE Computer Society, 2008
Series
International Conference on VLSI Design. Proceedings, ISSN 1063-9667
Keywords
embedded systems, worst-case execution time analysis, WCET, distributed systems, system-on-chip, SOC, scheduling
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-39303 (URN)10.1109/VLSI.2008.33 (DOI)000253939700024 ()47838 (Local ID)0-7695-3083-4 (ISBN)978-0-7695-3083-3 (ISBN)47838 (Archive number)47838 (OAI)
Conference
21st International Conference on VLSI Design (VLSID 2008), 4-8 January 2008, Hyderabad, India
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-13
Rosén, J., Andrei, A., Eles, P. I. & Peng, Z. (2007). Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip. In: 28th IEEE Real-Time Systems Symposium RTSS07,2007: . Paper presented at 28th IEEE Real-Time Systems Symposium RTSS07 (pp. 49). Tucson, Arizona, USA: IEEE Computer Society Press
Open this publication in new window or tab >>Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
2007 (English)In: 28th IEEE Real-Time Systems Symposium RTSS07,2007, Tucson, Arizona, USA: IEEE Computer Society Press , 2007, p. 49-Conference paper, Published paper (Refereed)
Abstract [en]

In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. This has a huge impact on worst-case execution time (WCET) analysis and, in general, on the predictability of real-time applications implemented on such systems. As opposed to the WCET analysis performed for a single processor system, where the cache miss penalty is considered constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks' WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this paper we present an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures. The emphasis of this paper is on the bus scheduling policy and its optimization, which is of huge importance for the performance of such a predictable multiprocessor application.

Place, publisher, year, edition, pages
Tucson, Arizona, USA: IEEE Computer Society Press, 2007
Keywords
embedded systems, multiprocessor systems, memory transfers, bus scheduling, system-on-chip, worst-case execution time analysis, WCET
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-39294 (URN)10.1109/RTSS.2007.24 (DOI)47827 (Local ID)978-0-7695-3062-8 (ISBN)47827 (Archive number)47827 (OAI)
Conference
28th IEEE Real-Time Systems Symposium RTSS07
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-13
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