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Qureshi, Fahad
Publications (10 of 13) Show all publications
Garrido Gálvez, M., Qureshi, F. & Gustafsson, O. (2014). Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI). IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 61(7), 2002-2012
Open this publication in new window or tab >>Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI)
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 7, p. 2002-2012Article in journal (Refereed) Published
Abstract [en]

This paper presents a new approach to design multiplierless constant rotators. The approach is based on a combined coefficient selection and shift-and-add implementation (CCSSI) for the design of the rotators. First, complete freedom is given to the selection of the coefficients, i.e., no constraints to the coefficients are set in advance and all the alternatives are taken into account. Second, the shift-and-add implementation uses advanced single constant multiplication (SCM) and multiple constant multiplication (MCM) techniques that lead to low-complexity multiplierless implementations. Third, the design of the rotators is done by a joint optimization of the coefficient selection and shift-and-add implementation. As a result, the CCSSI provides an extended design space that offers a larger number of alternatives with respect to previous works. Furthermore, the design space is explored in a simple and efficient way. The proposed approach has wide applications in numerous hardware scenarios. This includes rotations by single or multiple angles, rotators in single or multiple branches, and different scaling of the outputs. Experimental results for various scenarios are provided. In all of them, the proposed approach achieves significant improvements with respect to state of the art.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2014
Keywords
Adder minimization; combined coefficient selection and shift-and-add implementation (CCSSI); complex multiplier; fast Fourier transform; multiple constant multiplication (MCM); rotation; shift-and-add
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-109385 (URN)10.1109/TCSI.2014.2304664 (DOI)000339045500010 ()
Available from: 2014-08-15 Created: 2014-08-15 Last updated: 2019-06-28Bibliographically approved
Qureshi, F., Garrido, M. & Gustafsson, O. (2013). Unified architecture for 2, 3, 4, 5, and 7-point DFTs based on Winograd Fourier transform algorithm. Electronics Letters, 49(5), 348-U60
Open this publication in new window or tab >>Unified architecture for 2, 3, 4, 5, and 7-point DFTs based on Winograd Fourier transform algorithm
2013 (English)In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 49, no 5, p. 348-U60Article in journal (Refereed) Published
Abstract [en]

A unified hardware architecture that can be reconfigured to calculate 2, 3, 4, 5, or 7-point DFTs is presented. The architecture is based on the Winograd Fourier transform algorithm and the complexity is equal to a 7-point DFT in terms of adders/subtractors and multipliers plus only seven multiplexers introduced to enable reconfigurability. The processing element finds potential use in memory-based FFTs, where non-power-of-two sizes are required such as in DMB-T.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-74760 (URN)10.1049/el.2012.0577 (DOI)000318546200025 ()
Available from: 2012-02-07 Created: 2012-02-07 Last updated: 2019-06-28Bibliographically approved
Qureshi, F. (2012). Optimization of Rotations in FFTs. (Doctoral dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Optimization of Rotations in FFTs
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The aims of this thesis are to reduce the complexity and increasethe accuracy of rotations carried out inthe fast Fourier transform (FFT) at algorithmic and arithmetic level.In FFT algorithms, rotations appear after every hardware stage, which are alsoreferred to as twiddle factor multiplications.

At algorithmic level, the focus is on the development and analysisof FFT algorithms. With this goal, a new approach based on binary tree decompositionis proposed. It uses the Cooley Tukey algorithm to generate a large number ofFFT algorithms. These FFT algorithms have identical butterfly operations and data flow but differ inthe value of the rotations. Along with this, a technique for computing the indices of the twiddle factors based on the binary tree representation has been proposed. We have analyzed thealgorithms in terms of switching activity, coefficient memory size, number of non-trivial multiplicationsand round-off noise. These parameters have impact on the power consumption, area, and accuracy of the architecture.Furthermore, we have analyzed some specific cases in more detail for subsets of the generated algorithms.

At arithmetic level, the focus is on the hardware implementation of the rotations.These can be implemented using a complex multiplier,the CORDIC algorithm, and constant multiplications. Architectures based on the CORDIC and constant multiplication use shift and add operations, whereas the complex multiplication generally uses four real multiplications and two adders.The sine and cosine coefficients of the rotation angles fora complex multiplier are normally stored in a memory.The implementation of the coefficient memory is analyzed and the best possible approaches are analyzed.Furthermore, a number of twiddle factor multiplication architectures based on constant multiplications is investigated and proposed. In the first approach, the number of twiddle factor coefficients is reduced by trigonometric identities. By considering the addition aware quantization method, the accuracy and adder count of the coefficients are improved. A second architecture based on scaling the rotations such that they no longer have unity gain is proposed. This results in twiddle factor multipliers with even lower complexity and/or higher accuracy compared to the first proposed architecture.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2012. p. 49
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1423
Keywords
Discrete Fourier transform, Fast Fourier transform, twiddle factor multiplication
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-74702 (URN)978-91-7519-973-3 (ISBN)
Public defence
2012-03-01, Visionen, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2012-02-07 Created: 2012-02-05 Last updated: 2017-06-12Bibliographically approved
Qureshi, F. & Gustafsson, O. (2011). Generation of All Radix-2 Fast Fourier Transform Algorithms Using Binary Trees and Its Analysis. In: Proceedings of ECCTD 2011: 20th EuropeanConference on Circuit Theory and Design (ECCTD): . Paper presented at 20th European Conference on Circuit Theory and Design (ECCTD), 29-31 August, Linköping, Sweden (pp. 677-680). IEEE
Open this publication in new window or tab >>Generation of All Radix-2 Fast Fourier Transform Algorithms Using Binary Trees and Its Analysis
2011 (English)In: Proceedings of ECCTD 2011: 20th EuropeanConference on Circuit Theory and Design (ECCTD), IEEE , 2011, p. 677-680Conference paper, Published paper (Refereed)
Abstract [en]

In this work a systematic method to generate all possible fast Fourier transform (FFT) algorithms is proposed based on the relation to binary trees. The binary tree is used to represent the decomposition of a discrete Fourier transform (DFT) into sub-DFTs. The radix is adaptively changed according to compute sub-DFTs in proposed decomposition. In this work we determine the number of possible algorithms for 2n-point FFTs with radix-2 butterfly operation and propose a simple method to determine the twiddle factor indices for each algorithm based on the binary tree representation.

Place, publisher, year, edition, pages
IEEE, 2011
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-74756 (URN)10.1109/ECCTD.2011.6043634 (DOI)978-1-4577-0616-5 (ISBN)978-1-4577-0617-2 (ISBN)
Conference
20th European Conference on Circuit Theory and Design (ECCTD), 29-31 August, Linköping, Sweden
Note

The status of this article was before publishing Manuscript.

Available from: 2012-02-07 Created: 2012-02-07 Last updated: 2017-05-31Bibliographically approved
Qureshi, F. & Gustafsson, O. (2011). Low-Complexity Constant Multiplication Based on Trigonometric Identities with Applications to FFTs. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E94A(11), 2361-2368
Open this publication in new window or tab >>Low-Complexity Constant Multiplication Based on Trigonometric Identities with Applications to FFTs
2011 (English)In: IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, ISSN 0916-8508, E-ISSN 1745-1337, Vol. E94A, no 11, p. 2361-2368Article in journal (Refereed) Published
Abstract [en]

In this work we consider optimized twiddle factor multipliers based on shift-and-add-multiplication. We propose a low-complexity structure for twiddle factors with a resolution of 32 points. Furthermore, we propose a slightly modified version of a previously reported multiplier for a resolution of 16 points with lower round-off noise. For completeness we also include results on optimal coefficients for eight-points resolution. We perform finite word length analysis for both coefficients and round-off errors and derive optimized coefficients with minimum complexity for varying requirements.

Place, publisher, year, edition, pages
Institute of Electronics, Information and Communication Engineers, 2011
Keywords
complex multiplier, FFT, constant multiplication, shift-and-add multiplication
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-72819 (URN)10.1587/transfun.E94.A.2361 (DOI)000296673300038 ()
Note

Funding Agencies|Higher Education Commission, Pakistan||Linkoping University, Sweden||

Available from: 2011-12-08 Created: 2011-12-08 Last updated: 2017-12-08
Athar, S., Gustafsson, O., Qureshi, F. & Kale, I. (2011). On the efficient computation of single-bit input word length pipelined FFTs. IEICE Electronics Express, 8(17), 1437-1443
Open this publication in new window or tab >>On the efficient computation of single-bit input word length pipelined FFTs
2011 (English)In: IEICE Electronics Express, ISSN 1349-2543, E-ISSN 1349-2543, Vol. 8, no 17, p. 1437-1443Article in journal (Refereed) Published
Abstract [en]

This letter describes an efficient architecture for the computation of fast Fourier transform (FFT) algorithms with single-bit input. The proposed architecture is aimed for the first stages of pipelined FFT architectures, processing one sample per clock cycle, hence making it suiable for real-time FFT computation. Since natural input order pipeline FFTs use large memories in the early stages, it is important to keep the word length shorter in the beginning of the pipeline. By replacing the initial butterflies and rotators of an architecture with that of the proposed block, the memory requirements can be significantly reduced. Comparisons with the commonly used single delay feedback (SDF) architecture show that more than 50% of the required memory can be saved in some cases.

Place, publisher, year, edition, pages
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, KIKAI-SHINKO-KAIKAN BLDG MINATO-KU SHIBAKOEN 3 CHOME, TOKYO, 105, JAPAN, 2011
Keywords
FFT algorithm, complexity, single-bit, word length
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-71646 (URN)10.1587/elex.8.1437 (DOI)000295835400011 ()
Note

Funding Agencies|NED University, Pakistan||Higher Education Commission, Pakistan||CENIIT at Linkoping University, Sweden||Innovative Navigation using new GNSS Signals with Hybridised Technologies (INSIGHT)||UK Engineering and Physical Sciences Research Council (EPSRC)||

Available from: 2011-10-27 Created: 2011-10-27 Last updated: 2017-12-08
Qureshi, F., Alam, S. A. & Gustafsson, O. (2010). 4-k point FFT algorithms based on optimized twiddle factor multiplication for FPGAs. In: The Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Shanghai, Sept. 22-24, 2010.: . Paper presented at 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010; Shanghai; China (pp. 225-228).
Open this publication in new window or tab >>4-k point FFT algorithms based on optimized twiddle factor multiplication for FPGAs
2010 (English)In: The Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Shanghai, Sept. 22-24, 2010., 2010, p. 225-228Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-65908 (URN)10.1109/PRIMEASIA.2010.5604921 (DOI)978-1-4244-6736-5 (ISBN)978-1-4244-6735-8 (ISBN)
Conference
2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010; Shanghai; China
Available from: 2011-03-07 Created: 2011-02-25 Last updated: 2016-05-04Bibliographically approved
Gustafsson, O. & Qureshi, F. (2010). Addition Aware Quantization for Low Complexity and High Precision Constant Multiplication. IEEE Signal Processing Letters, 17(2), 173-176
Open this publication in new window or tab >>Addition Aware Quantization for Low Complexity and High Precision Constant Multiplication
2010 (English)In: IEEE Signal Processing Letters, ISSN 1070-9908, E-ISSN 1558-2361, Vol. 17, no 2, p. 173-176Article in journal (Refereed) Published
Abstract [en]

Multiplication by constants can be efficiently realized using shifts, additions, and subtractions. In this work we consider how to select a fixed-point value for a real valued, rational, or floating-point coefficient to obtain a low-complexity realization. It is shown that the process, denoted addition aware quantization, often can determine coefficients that has as low complexity as the rounded value, but with a smaller approximation error by searching among coefficients with a longer wordlength.

Place, publisher, year, edition, pages
IEEE, 2010
Keywords
Addition; constant multiplication; quantization; subtraction
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-52893 (URN)10.1109/LSP.2009.2036384 (DOI)000272844400001 ()
Note

©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Oscar Gustafsson and Fahad Qureshi, Addition Aware Quantization for Low Complexity and High Precision Constant Multiplication, 2010, IEEE Signal Processing Letters, (17), 2, 173-176. http://dx.doi.org/10.1109/LSP.2009.2036384

Available from: 2010-01-13 Created: 2010-01-12 Last updated: 2017-12-12Bibliographically approved
Qureshi, F., Garrido, M. & Gustafsson, O. (2010). Alternatives for Low-Complexity Complex Rotators. In: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems, (ICECS 2010), Athens, Dec-12-15, 2010. Paper presented at The 17th IEEE International Conference on Electronics, Circuits, and Systems, (ICECS 2010), Athens, Dec-12-15, 2010 (pp. 17-20). IEEE
Open this publication in new window or tab >>Alternatives for Low-Complexity Complex Rotators
2010 (English)In: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems, (ICECS 2010), Athens, Dec-12-15, 2010, IEEE , 2010, p. 17-20Conference paper, Published paper (Refereed)
Abstract [en]

Complex rotations find use in common transforms such as the Discrete Cosine Transform (DCT) and the Discrete Fourier Transform (DFT). In this work we consider low-complexity realization of constant angle rotators based on shifts, adders, and subtracters. The results show that redundant CORDIC and scaled constant multiplication are providing the best results, depending on which angle is considered. It is also shown that the precision can vary several bits using the same number of adders and subtracters, and, hence, the correct choice of rotator architecture is crucial for a low-complexity realization.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-65909 (URN)10.1109/ICECS.2010.5724443 (DOI)
Conference
The 17th IEEE International Conference on Electronics, Circuits, and Systems, (ICECS 2010), Athens, Dec-12-15, 2010
Note
©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Fahad Qureshi, Mario Garrido and Oscar Gustafsson, Alternatives for Low-Complexity Complex Rotators, 2010, The 17th IEEE International Conference on Electronics, Circuits, and Systems, (ICECS 2010), Athens, Dec-12-15, 2010. Available from: 2011-03-07 Created: 2011-02-25 Last updated: 2015-03-11Bibliographically approved
Qureshi, F. & Gustafsson, O. (2010). Twiddle factor memory switching activity analysis of radix-22 and equivalent FFT algorithms. In: The IEEE International Symposium on Circuits and Systems (ISCAS) , Paris, 2010.: . Paper presented at 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010; Paris; France (pp. 4145-4148). IEEE
Open this publication in new window or tab >>Twiddle factor memory switching activity analysis of radix-22 and equivalent FFT algorithms
2010 (English)In: The IEEE International Symposium on Circuits and Systems (ISCAS) , Paris, 2010., IEEE , 2010, p. 4145-4148Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we propose equivalent radix-22 algorithms and evaluate them based on twiddle factor switching activity for a single delay feedback pipelined FFT architecture. These equivalent pipeline FFT algorithms have the same number of complex multipliers with the same resolution as the radix-22. It is shown that the twiddle factor switching activity of the equivalent algorithms is reduced with up to 40% for some of the equivalent algorithms derived for N = 256.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-65911 (URN)10.1109/ISCAS.2010.5537605 (DOI)978-1-4244-5309-2 (ISBN)978-1-4244-5308-5 (ISBN)
Conference
2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010; Paris; France
Note

©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Fahad Qureshi and Oscar Gustafsson, Twiddle factor memory switching activity analysis of radix-22 and equivalent FFT algorithms, 2010, The IEEE International Symposium on Circuits and Systems (ISCAS) , Paris, 2010, 4145-4148.

Available from: 2011-03-07 Created: 2011-02-25 Last updated: 2015-03-11Bibliographically approved
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