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BETA
Abbas, Muhammad
Alternative names
Publications (10 of 11) Show all publications
Fowler, S., Sarfraz, J., Abbas, M. M. & Angelakis, V. (2015). Gaussian semi-Markov Model based on Real Video Multimedia Traffic. In: IEEE (Ed.), IEEE International Conference on Communications Communications (ICC) 2015: . Paper presented at IEEE ICC 2015 - Communications Software, Services and Multimedia Applications Symposium, 8-12 June 2015, London, UK (pp. 6971-6976). IEEE Press
Open this publication in new window or tab >>Gaussian semi-Markov Model based on Real Video Multimedia Traffic
2015 (English)In: IEEE International Conference on Communications Communications (ICC) 2015 / [ed] IEEE, IEEE Press, 2015, p. 6971-6976Conference paper, Published paper (Refereed)
Abstract [en]

The 3rd Generation Partnership Project (3GPP) introduced the new radio access technology, LTE (Long Term Evolution) and LTE-Advanced, which has the capability to provide larger bandwidth and low latencies on a wireless network in order to fulfill the demand of Users' Equipment (UEs) with acceptable Quality of Service (QoS). One of the data-heavy applications that has exploded on the market is Video. This calls for accurate modeling of video traffic. To ensure the quality and correctness of complex systems with Video traffic, it is important to evaluate the behavior of the traffic in the heterogeneous environment. This paper presents measurements on LTE Video traffic which were performed in a real environment. We derived a semi-Markov model which accurately reproduces the statistics of composite Video measurements over LTE network.

Place, publisher, year, edition, pages
IEEE Press, 2015
Series
IEEE International Conference on Communications, ISSN 1550-3607
Keywords
LTE; semi-Markov; lognormal; Gaussian Mixture Model; Real Video Traffic; Empirical Data
National Category
Telecommunications
Identifiers
urn:nbn:se:liu:diva-117277 (URN)10.1109/ICC.2015.7249437 (DOI)000371708107033 ()
Conference
IEEE ICC 2015 - Communications Software, Services and Multimedia Applications Symposium, 8-12 June 2015, London, UK
Projects
EC-FP7 Marie Curie CIG grant, Proposal number: 294182;European Unions Seventh Framework Programme (FP7/2007-2013) under grant agreement no [609094 RERUM].
Funder
EU, FP7, Seventh Framework Programme, 609094EU, FP7, Seventh Framework Programme, 294182
Available from: 2015-08-22 Created: 2015-04-22 Last updated: 2016-04-20Bibliographically approved
Abbas, M., Gustafsson, O. & Johansson, H. (2013). On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 60(4), 926-937
Open this publication in new window or tab >>On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure
2013 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 4, p. 926-937Article in journal (Refereed) Published
Abstract [en]

In this paper, the fixed-point implementation of adjustable fractional-delay filters using the Farrow structure is considered. Based on the observation that the sub-filters approximate differentiators, closed-form expressions for the L-2-norm scaling values at the outputs of each sub-filter as well as at the inputs of each delay multiplier are derived. The scaling values can then be used to derive suitable word lengths by also considering the round-off noise analysis and optimization. Different approaches are proposed to derive suitable word lengths including one based on integer linear programming, which always gives an optimal allocation. Finally, a new approach for multiplierless implementation of the sub-filters in the Farrow structure is suggested. This is shown to reduce register complexity and, for most word lengths, require less number of adders and subtracters when compared to existing approaches.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2013
Keywords
Farrow structure; fractional-delay digital filter; multiplierless; round-off noise; scaling; word length optimization
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-96157 (URN)10.1109/TCSI.2013.2244272 (DOI)000317005400011 ()
Available from: 2013-08-14 Created: 2013-08-14 Last updated: 2017-12-06
Abbas, M. (2012). On the Implementation of Integer and Non-Integer Sampling Rate Conversion. (Doctoral dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>On the Implementation of Integer and Non-Integer Sampling Rate Conversion
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The main focus in this thesis is on the aspects related to the implementation of integer and non-integer sampling rate conversion (SRC). SRC is used in many communication and signal processing applications where two signals or systems having different sampling rates need to be interconnected. There are two basic approaches to deal with this problem. The first is to convert the signal to analog and then re-sample it at the desired rate. In the second approach, digital signal processing techniques are utilized to compute values of the new samples from the existing ones. The former approach is hardly used since the latter one introduces less noise and distortion. However, the implementation complexity for the second approach varies for different types of conversion factors. In this work, the second approach for SRC is considered and its implementation details are explored. The conversion factor in general can be an integer, a ratio of two integers, or an irrational number. The SRC by an irrational numbers is impractical and is generally stated for the completeness. They are usually approximated by some rational factor.

The performance of decimators and interpolators is mainly determined by the filters, which are there to suppress aliasing effects or removing unwanted images. There are many approaches for the implementation of decimation and interpolation filters, and cascaded integrator comb (CIC) filters are one of them. CIC filters are most commonly used in the case of integer sampling rate conversions and often preferred due to their simplicity, hardware efficiency, and relatively good anti-aliasing (anti-imaging) characteristics for the first (last) stage of a decimation (interpolation). The multiplierless nature, which generally yields to low power consumption, makes CIC filters well suited for performing conversion at higher rate. Since these filters operate at the maximum sampling frequency, therefore, are critical with respect to power consumption. It is therefore necessary to have an accurate and efficient ways and approaches that could be utilized to estimate the power consumption and the important factors that are contributing to it. Switching activity is one such factor. To have a high-level estimate of dynamic power consumption, switching activity equations in CIC filters are derived, which may then be used to have an estimate of the dynamic power consumption. The modeling of leakage power is also included, which is an important parameter to consider since the input sampling rate may differ several orders of magnitude. These power estimates at higher level can then be used as a feed-back while exploring multiple alternatives.

Sampling rate conversion is a typical example where it is required to determine the values between existing samples. The computation of a value between existing samples can alternatively be regarded as delaying the underlying signal by a fractional sampling period. The fractional-delay filters are used in this context to provide a fractional-delay adjustable to any desired value and are therefore suitable for both integer and non-integer factors. The structure that is used in the efficient implementation of a fractional-delay filter is know as Farrow structure or its modifications. The main advantage of the Farrow structure lies in the fact that it consists of fixed finite-impulse response (FIR) filters and there is only one adjustable fractional-delay parameter, used to evaluate a polynomial with the filter outputs as coefficients. This characteristic of the Farrow structure makes it a very attractive structure for the implementation. In the considered fixed-point implementation of the Farrow structure, closed-form expressions for suitable word lengths are derived based on scaling and round-off noise. Since multipliers share major portion of the total power consumption, a matrix-vector multiple constant multiplication approach is proposed to improve the multiplierless implementation of FIR sub-filters.

The implementation of the polynomial part of the Farrow structure is investigated by considering the computational complexity of different polynomial evaluation schemes. By considering the number of operations of different types, critical path, pipelining complexity, and latency after pipelining, high-level comparisons are obtained and used to short list the suitable candidates. Most of these evaluation schemes require the explicit computation of higher order power terms. In the parallel evaluation of powers, redundancy in computations is removed by exploiting any possible sharing at word level and also at bit level. As a part of this, since exponents are additive under multiplication, an ILP formulation for the minimum addition sequence problem is proposed.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2012. p. 65
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1420
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-73722 (URN)978-91-7519-980-1 (ISBN)
Public defence
2012-02-09, Visionen, B-building, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2012-01-17 Created: 2012-01-12 Last updated: 2015-03-11Bibliographically approved
Abbas, M. & Gustafsson, O. (2011). Computational and Implementation Complexity of Polynomial Evaluation Schemes. In: Proceedings of NORCHIP, 2011 Date:14-15 Nov. 2011. Paper presented at NORCHIP 2011. The Nordic Microelectronics event, 29th Norchip Conference 14-15 November 2011, Lund, Sweden (pp. 1-6). IEEE conference proceedings
Open this publication in new window or tab >>Computational and Implementation Complexity of Polynomial Evaluation Schemes
2011 (English)In: Proceedings of NORCHIP, 2011 Date:14-15 Nov. 2011, IEEE conference proceedings, 2011, p. 1-6Conference paper, Published paper (Refereed)
Abstract [en]

In this work, we consider the computational complexity of different polynomial evaluation schemes. By considering the number of operations of different types, critical path, pipelining complexity, and latency after pipelining, high-level comparisons are obtained. These can then be used to short list suitable candidates for an implementation given the specifications. Not only multiplications are considered, but they are divided into data-data multiplications, squarers, and data-coefficient multiplications, as the latter can be optimized depending on implementation architecture and application.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2011
Keywords
Adders, Computer architecture, Delay, Filtering algorithms, ISO, Pipeline processing, Polynomials
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-73935 (URN)10.1109/NORCHP.2011.6126735 (DOI)978-1-4577-0515-1 (ISBN)978-1-4577-0514-4 (ISBN)
Conference
NORCHIP 2011. The Nordic Microelectronics event, 29th Norchip Conference 14-15 November 2011, Lund, Sweden
Available from: 2012-01-17 Created: 2012-01-17 Last updated: 2015-03-11Bibliographically approved
Abbas, M., Gustafsson, O. & Blad, A. (2010). Low-Complexity Parallel Evaluation of Powers Exploiting Bit-Level Redundancy. In: Michael B. Matthews (Ed.), Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010. Paper presented at Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 , Pacific Grove, CA, USA (pp. 1168-1172). Washington, DC, USA: IEEE Computer Society
Open this publication in new window or tab >>Low-Complexity Parallel Evaluation of Powers Exploiting Bit-Level Redundancy
2010 (English)In: Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 / [ed] Michael B. Matthews, Washington, DC, USA: IEEE Computer Society , 2010, p. 1168-1172Conference paper, Published paper (Refereed)
Abstract [en]

In this work, we investigate the problem of computing any requested set of power terms in parallel using summations trees. This problem occurs in applications like polynomial approximation, Farrow filters (polynomial evaluation part) etc. In the proposed technique, the partial product of each power term is initially computed independently. A redundancy check is then made in each and among all partial products matrices at bit level. The redundancy here relates to the fact that same three partial products may be present in more than one columns, and, hence, can be mapped to the same full adder. The proposed algorithm is tested for different sets of powers and wordlengths to exploit the sharing potential.

Place, publisher, year, edition, pages
Washington, DC, USA: IEEE Computer Society, 2010
Series
Asilomar Conference on Signals, Systems and Computers. Conference Record, ISSN 1058-6393
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-70453 (URN)10.1109/ACSSC.2010.5757714 (DOI)978-1-4244-9722-5 (ISBN)
Conference
Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 , Pacific Grove, CA, USA
Available from: 2011-09-20 Created: 2011-09-08 Last updated: 2015-03-11Bibliographically approved
Abbas, M., Gustafsson, O. & Wanhammar, L. (2010). Power Estimation of Recursive and Non-Recursive CIC Filters Implemented in Deep-Submicron Technology. In: Proceedings of International Conference on Green Circuits and Systems (ICGCS), 2010, Date: 21-23 June, 2010. Paper presented at International Conference on Green Circuits and Systems (ICGCS), June 21–23, Shanghai, China (pp. 221-225). IEEE
Open this publication in new window or tab >>Power Estimation of Recursive and Non-Recursive CIC Filters Implemented in Deep-Submicron Technology
2010 (English)In: Proceedings of International Conference on Green Circuits and Systems (ICGCS), 2010, Date: 21-23 June, 2010, IEEE , 2010, p. 221-225Conference paper, Published paper (Refereed)
Abstract [en]

The power modeling of different realizations of cascaded integrator-comb (CIC) decimation filters has been a subject of several recent works. In this work we have extended these with modeling of leakage power, which is an important factor since the input sample rate may differ several orders of magnitude. Furthermore, we have pointed out the importance of the input wordlength on the comparison of recursive and nonrecursive implementations.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-70451 (URN)10.1109/ICGCS.2010.5543063 (DOI)978-1-4244-6877-5 (ISBN)978-1-4244-6876-8 (ISBN)
Conference
International Conference on Green Circuits and Systems (ICGCS), June 21–23, Shanghai, China
Available from: 2011-09-20 Created: 2011-09-08 Last updated: 2015-03-11Bibliographically approved
Abbas, M. & Gustafsson, O. (2010). Switching Activity Estimation of CIC Filter Integrators. In: Proceedings of Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2010, Date:22-24 Sept. 2010. Paper presented at Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 22-24 September, Shanghai, China (pp. 21-24). IEEE
Open this publication in new window or tab >>Switching Activity Estimation of CIC Filter Integrators
2010 (English)In: Proceedings of Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2010, Date:22-24 Sept. 2010, IEEE , 2010, p. 21-24Conference paper, Published paper (Refereed)
Abstract [en]

In this work, a method for estimation of the switching activity in integrators is presented. To achieve low power, it is always necessary to develop accurate and efficient methods to estimate the switching activity. The switching activities are then used to estimate the power consumption. In our work, the switching activity is first estimated for the general purpose integrators and then it is extended for the estimation of switching activity in cascaded integrators in CIC filters.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-70452 (URN)10.1109/PRIMEASIA.2010.5604971 (DOI)978-1-4244-6736-5 (ISBN)978-1-4244-6735-8 (ISBN)
Conference
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 22-24 September, Shanghai, China
Note
©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. MUHAMMAD ABBAS and Oscar Gustafsson, Switching Activity Estimation of CIC Filter Integrators, 2010, Asia Pacific Conf. on Postgraduate Research in Microelectronics and Electronics, Shanghai, China. http://dx.doi.org/10.1109/PRIMEASIA.2010.5604971 Available from: 2011-09-20 Created: 2011-09-08 Last updated: 2015-03-11Bibliographically approved
Abbas, M., Gustafsson, O. & Johansson, H. (2009). Scaling of fractional delay filters based on the Farrow structure. In: Proceedings of IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009. Paper presented at IEEE International Symposium on Circuits and Systems, 24-27 May 2009, Taipei,Taiwan (pp. 489-492). Piscataway: IEEE
Open this publication in new window or tab >>Scaling of fractional delay filters based on the Farrow structure
2009 (English)In: Proceedings of IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009, Piscataway: IEEE , 2009, p. 489-492Conference paper, Published paper (Refereed)
Abstract [en]

In this work we consider scaling of fractional delay filters using the Farrow structure. Based on the observation that the subfilters approximate the Taylor expansion of a differentiator, we derive estimates of the L2-norm scaling values at the outputs of each subfilter as well as at the inputs of each delay multiplier. The scaling values can then be used to derive suitable wordlengths in a fixed-point implementation.

Place, publisher, year, edition, pages
Piscataway: IEEE, 2009
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-51070 (URN)10.1109/ISCAS.2009.5117792 (DOI)000275929800123 ()978-1-4244-3827-3 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems, 24-27 May 2009, Taipei,Taiwan
Available from: 2009-10-15 Created: 2009-10-15 Last updated: 2018-09-01Bibliographically approved
Abbas, M., Qureshi, F., Ullah Sheikh, Z., Gustafsson, O., Johansson, H. & Johansson, K. (2008). Comparison of Multiplierless Implementation of Nonlinear-Phase Versus Linear-Phase FIR filters. Paper presented at 42ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, ISSN 1058-6393. IEEE
Open this publication in new window or tab >>Comparison of Multiplierless Implementation of Nonlinear-Phase Versus Linear-Phase FIR filters
Show others...
2008 (English)Conference paper, Published paper (Refereed)
Abstract [en]

FIR filters are often used because of their linear-phase response. However, there are certain applications where the linear-phase property is not required, such as signal energy estimation, but IIR filters can not be used due to the limitation of sample rate imposed by the recursive algorithm. In this work, we discuss multiplierless implementation of minimum order, and therefore nonlinear-phase, FIR filters and compare it to the linear-phase counterpart.

Place, publisher, year, edition, pages
IEEE, 2008
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-54167 (URN)10.1109/ACSSC.2008.5074475 (DOI)000274551000114 ()978-1-4244-2940-0 (ISBN)
Conference
42ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, ISSN 1058-6393
Available from: 2011-09-20 Created: 2010-02-26 Last updated: 2015-03-11Bibliographically approved
Abbas, M. & Gustafsson, O.Integer Linear Programming Modeling of Addition Sequences With Additional Constraints for Evaluation of Power Terms.
Open this publication in new window or tab >>Integer Linear Programming Modeling of Addition Sequences With Additional Constraints for Evaluation of Power Terms
(English)Manuscript (preprint) (Other academic)
Abstract [en]

In this work, an integer linear programming (ILP) based model is proposed for the computation of a minimal cost addition sequence for a given set of integers. Since exponents are additive under multiplication, the minimal length addition sequence will provide an optimal solution for the evaluation of a requested set of power terms. This in turn finds application in, e.g., window-based exponentiation for cryptography and polynomial evaluation. Not only is an optimal model proposed, the model is extended to consider different costs for multipliers and squarers as well as controlling the depth of the resulting addition sequence.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-73936 (URN)
Available from: 2012-01-17 Created: 2012-01-17 Last updated: 2015-03-11Bibliographically approved
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