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Wikner, Jacob
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Publications (10 of 79) Show all publications
Harikumar, P., Wikner, J. & Alvandpour, A. (2016). A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications. IEEE Transactions on Circuits and Systems - II - Express Briefs, 63(8), 743-747
Open this publication in new window or tab >>A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications
2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, p. 743-747Article in journal (Refereed) Published
Abstract [en]

This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016
Keywords
Analog-to-digital converter, ADC, successive approximation register, SAR, ultra-low-voltage
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122729 (URN)10.1109/TCSII.2016.2531099 (DOI)000381440000007 ()978-1-4799-9877-7 (ISBN)
Note

At the time for thesis presentation publication was in status: Manuscript

Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2017-12-01Bibliographically approved
Hassanli, K., Masoud Sayedi, S. & Wikner, J. (2016). A compact, low-power, and fast pulse-width modulation based digital pixel sensor with no bias circuit. Sensors and Actuators A-Physical, 244, 243-251
Open this publication in new window or tab >>A compact, low-power, and fast pulse-width modulation based digital pixel sensor with no bias circuit
2016 (English)In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 244, p. 243-251Article in journal (Refereed) Published
Abstract [en]

A high-speed and compact in-pixel light-to-time converter (LTC), with low power consumption and wide dynamic range is presented. By using the proposed LTC, a digital pixel sensor (DPS) based on a pulse width modulation (PWM) scheme has been designed and fabricated in a standard 180-nm, single-poly, six-metal complementary metal oxide semiconductor (CMOS) technology. The prototype chip consists of a 16 x 16 pixel array with an individual pixel size of 21 x 21 mu m(2) and a fill factor of 39% in the 180-nm CMOS technology. Experimental results show that the circuit operates at supply voltages down to 800 mV and achieves an overall dynamic range of more than 140 dB. The power consumption at 800 mV supply and room light intensity is approximately 2.85 nW. (C) 2016 Elsevier B.V. All rights reserved.

Place, publisher, year, edition, pages
ELSEVIER SCIENCE SA, 2016
Keywords
PWM based digital pixel sensor; Low-power CMOS image sensor; Pixel-level analog-to-digital converter (ADC); High speed imaging; Wide dynamic range imager
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-130062 (URN)10.1016/j.sna.2016.04.049 (DOI)000377324000030 ()
Available from: 2016-07-06 Created: 2016-07-06 Last updated: 2017-11-28
Berggren, M., Simon, D., Nilsson, D., Dyreklev, P., Norberg, P., Nordlinder, S., . . . Hentzell, H. (2016). Browsing the Real World using Organic Electronics, Si-Chips, and a Human Touch.. Advanced Materials, 28(10), 1911-1916
Open this publication in new window or tab >>Browsing the Real World using Organic Electronics, Si-Chips, and a Human Touch.
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2016 (English)In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 28, no 10, p. 1911-1916Article in journal (Refereed) Published
Abstract [en]

Organic electronics have been developed according to an orthodox doctrine advocating "all-printed, "all-organic and "ultra-low-cost primarily targeting various e-paper applications. In order to harvest from the great opportunities afforded with organic electronics potentially operating as communication and sensor outposts within existing and future complex communication infrastructures, high-quality computing and communication protocols must be integrated with the organic electronics. Here, we debate and scrutinize the twinning of the signal-processing capability of traditional integrated silicon chips with organic electronics and sensors, and to use our body as a natural local network with our bare hand as the browser of the physical world. The resulting platform provides a body network, i.e., a personalized web, composed of e-label sensors, bioelectronics, and mobile devices that together make it possible to monitor and record both our ambience and health-status parameters, supported by the ubiquitous mobile network and the resources of the "cloud".

Place, publisher, year, edition, pages
Wiley-VCH, 2016
National Category
Communication Systems Other Computer and Information Science
Identifiers
urn:nbn:se:liu:diva-125994 (URN)10.1002/adma.201504301 (DOI)000372308700001 ()26742807 (PubMedID)
Note

Funding agencies:  Knut and Alice Wallenberg Foundation; Onnesjo Foundation; VINNOVA; Swedish Foundation for Strategic Research

Available from: 2016-03-11 Created: 2016-03-11 Last updated: 2018-01-10
Kazim, M. I. & Wikner, J. (2016). Design of a Sub-mW Front-End Amplifier for Capacitive BCC Receiver in 65 nm CMOS. In: Proceedings of 2016 13th International Bhurban Conference on Applied Sciences and Technology (IBCAST): . Paper presented at 13th International Bhurban Conference on Applied Sciences and Technology (IBCAST), Islamabad, Pakistan, January 12-16, 2016 (pp. 607-610). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Design of a Sub-mW Front-End Amplifier for Capacitive BCC Receiver in 65 nm CMOS
2016 (English)In: Proceedings of 2016 13th International Bhurban Conference on Applied Sciences and Technology (IBCAST), Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 607-610Conference paper, Published paper (Refereed)
Abstract [en]

A low power front-end fully differential operational transconductance amplifier (OTA) has been designed in 65 nm CMOS technology which is suitable to receive low data rates upto 300 kbps for capacitive body coupled communication (BCC) channel. The current shunt current mirror OTA topology has been utilized in open loop configuration in the context of digital baseband architecture on the receiver side. The simulated resuts show that OTA achieves unity gain bandwidth (UGBW) of 200 MHz, dc gain of 40 dB, phase margin of 45 degree and rms integrated noise of 130 μV between 10 kHz to 150 MHz for 1.5 pF load capacitance and power consumption of approximately 250 μW. The OTA achieves high CMRR and PSRR (due to positive supply) of more than 120 dB at 100 Hz.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016
Series
Applied Sciences and Technology (IBCAST), 2016 13th International Bhurban Conference on, ISSN 2151-1403, E-ISSN 2151-1411
National Category
Computer Sciences Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-122837 (URN)10.1109/IBCAST.2016.7429940 (DOI)000384643000097 ()9781467391269 (ISBN)9781467391276 (ISBN)9781467391252 (ISBN)
Conference
13th International Bhurban Conference on Applied Sciences and Technology (IBCAST), Islamabad, Pakistan, January 12-16, 2016
Note

At the time for thesis presentation publication was in status: Manuscript

Available from: 2015-11-26 Created: 2015-11-26 Last updated: 2018-02-05Bibliographically approved
Harikumar, P. & Wikner, J. (2015). A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer. Integration, 50, 28-38
Open this publication in new window or tab >>A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
2015 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, p. 28-38Article in journal (Refereed) Published
Abstract [en]

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.

Place, publisher, year, edition, pages
Elsevier, 2015
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-111957 (URN)10.1016/j.vlsi.2015.01.002 (DOI)000357054300003 ()
Available from: 2014-11-11 Created: 2014-11-11 Last updated: 2017-12-05Bibliographically approved
Harikumar, P., Wikner, J. & Alvandpour, A. (2015). A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications. In: 2015 European Conference on Circuit Theory and Design (ECCTD): . Paper presented at 2015 European Conference on Circuit Theory and Design (ECCTD), August 24-26, Trondheim, Norway (pp. 13-16). IEEE
Open this publication in new window or tab >>A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications
2015 (English)In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 13-16Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68ï¿œ while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20oC +85oC].

Place, publisher, year, edition, pages
IEEE, 2015
Keywords
CMOS integrated circuits;analogue-digital conversion;mixed analogue-digital integrated circuits;operational amplifiers;silicon-on-insulator;PGA;SAR ADC;Si;UTBB FDSOI CMOS process;analog-mixed-signal circuits;continuous-time CMFB circuits;frequency 4.3 MHz;fully-differential OTA;gain 6 dB;gain 70 dB;operational transconductance amplifier;power 2.9 muW;programmable gain amplifier;reverse body bias;size 28 nm;temperature -20 degC to 85 degC;time 5.8 mus;ultrathin box and body fully-depleted silicon-on-insulator;voltage 1 V;word length 9 bit;Electronics packaging;Gain;Linearity;MOS devices;Resistors;Threshold voltage;Transistors
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122727 (URN)10.1109/ECCTD.2015.7300114 (DOI)000380498200096 ()978-1-4799-9877-7 (ISBN)
Conference
2015 European Conference on Circuit Theory and Design (ECCTD), August 24-26, Trondheim, Norway
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-09-25Bibliographically approved
Hassanli, K., Masoud Sayedi, S., Dehghani, R., Jalili, A. & Wikner, J. (2015). A highly sensitive, low-power, and wide dynamic range CMOS digital pixel sensor. Sensors and Actuators A-Physical, 236, 82-91
Open this publication in new window or tab >>A highly sensitive, low-power, and wide dynamic range CMOS digital pixel sensor
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2015 (English)In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 236, p. 82-91Article in journal (Refereed) Published
Abstract [en]

This paper proposes a new pixel-level light-to-frequency converter (LFC) that operates at a low supply voltage, and also offers low power consumption, low area, wide dynamic range, and high sensitivity. By using the proposed LFC, a digital pixel sensor (DPS) based on a pulse-frequency-modulation (PFM) scheme has been designed and fabricated. The prototype chip, including an array of 16 x 16 DPS with pixel size of 23 x 23 mu m(2) and 33.5% fill factor, was fabricated in a standard 180-nm CMOS technology. Experimental results show that the pixel operates with maintained output characteristics at supply voltages down to 1 V. The pixel sensor achieves an overall dynamic range of more than 142 dB and consumes 103 nW per pixel at a supply voltage of 1V at room light intensity. The sensitivity of the LFC is very high at the lower end of the light intensity compared to the higher end which enables the ability to capture clear images. (C) 2015 Elsevier B.V. All rights reserved.

Place, publisher, year, edition, pages
ELSEVIER SCIENCE SA, 2015
Keywords
CMOS image sensor; Digital pixel sensor; Light-to-frequency conversion; Pixel-level analog-to-digital converter (ADC); High speed imaging; Wide dynamic range
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-124520 (URN)10.1016/j.sna.2015.10.032 (DOI)000367483500010 ()
Available from: 2016-02-02 Created: 2016-02-01 Last updated: 2017-11-30
Kazim, M. I., Kazim, M. I. & Wikner, J. J. (2015). An Efficient Full-Wave Electromagnetic Analysis for Capacitive Body-Coupled Communication. International Journal of Antennas and Propagation, 2015, 15, Article ID 245621.
Open this publication in new window or tab >>An Efficient Full-Wave Electromagnetic Analysis for Capacitive Body-Coupled Communication
2015 (English)In: International Journal of Antennas and Propagation, ISSN 1687-5869, E-ISSN 1687-5877, Vol. 2015, p. 15-, article id 245621Article in journal (Refereed) Published
Abstract [en]

Measured propagation loss for capacitive body-coupled communication (BCC) channel (1 MHz to 60 MHz) is limitedly available in the literature for distances longer than 50 cm. This is either because of experimental complexity to isolate the earth-ground or design complexity in realizing a reliable communication link to assess the performance limitations of capacitive BCC channel. Therefore, an alternate efficient full-wave electromagnetic (EM) simulation approach is presented to realistically analyze capacitive BCC, that is, the interaction of capacitive coupler, the human body, and the environment all together. The presented simulation approach is first evaluated for numerical/human body variation uncertainties and then validated with measurement results from literature, followed by the analysis of capacitive BCC channel for twenty different scenarios. The simulation results show that the vertical coupler configuration is less susceptible to physiological variations of underlying tissues compared to the horizontal coupler configuration. The propagation loss is less for arm positions when they are not touching the torso region irrespective of the communication distance. The propagation loss has also been explained for complex scenarios formed by the ground-plane and the material structures (metals or dielectrics) with the human body. The estimated propagation loss has been used to investigate the link-budget requirement for designing capacitive BCC system in CMOS sub-micron technologies.

Keywords
Efficient Full-Wave Electromagnetic, Efficient Full-Wave EM, Full-Wave EM, Capacitive Body-Coupled Communication, Body-Coupled Communication, Vertical Coupler, Horizontal Coupler, Propagation Loss, Numerical technique, Analytical
National Category
Communication Systems
Identifiers
urn:nbn:se:liu:diva-118883 (URN)10.1155/2015/245621 (DOI)000356768000001 ()
Projects
VINNOVA
Funder
VINNOVA
Available from: 2015-06-04 Created: 2015-06-04 Last updated: 2017-12-04Bibliographically approved
Harikumar, P., Wikner, J. & Alvandpour, A. (2015). An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias. In: Proc. IEEE Nordic Circuits and Systems Conf. (NORCAS), Oslo, Norway, pp. 1-4, Oct. 2015: . Paper presented at 2015 NORCAS conference, IEEE Nordic Circuits and Systems Conference, 26-28 October, Oslo, Norway (pp. 1-4). IEEE
Open this publication in new window or tab >>An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias
2015 (English)In: Proc. IEEE Nordic Circuits and Systems Conf. (NORCAS), Oslo, Norway, pp. 1-4, Oct. 2015, IEEE , 2015, p. 1-4Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuoustime common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68o. Sufficient performance is maintained over process, supply voltage and temperature variations.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122728 (URN)10.1109/NORCHIP.2015.7364416 (DOI)000380441400063 ()978-1-4673-6576-5 (ISBN)
Conference
2015 NORCAS conference, IEEE Nordic Circuits and Systems Conference, 26-28 October, Oslo, Norway
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-09-16Bibliographically approved
Kazim, M. I., Cunha, B., Wikner, J. & Martins, R. (2015). Capacitive Body Coupled Communication: A Step Towards Reliable Short Range Wireless Technology.
Open this publication in new window or tab >>Capacitive Body Coupled Communication: A Step Towards Reliable Short Range Wireless Technology
2015 (English)Manuscript (preprint) (Other academic)
Abstract [en]

The paradigm of computation is currently changing from desktop computing towards ubiquitous computing by interfacing ambulatory devices with mobile phones/platforms. For an efficient implementation, ultra short range wireless network technologies, such as the body area network (BAN), are needed which could avoid the saturation of carrier frequencies, low power dissipation, and the electromagnetic interference. In this work, body coupled communication (BCC) based on capacitive reactive field has been  outlined as an important extension of BAN. It has been experimentally demonstrated as an alternative to traditional short range wireless communication based on radio frequency (RF) technologies. The concept of signal transmission through the capacitive BCC channel is explained using a lumped circuit model which is further supported by electromagnetic (EM) simulations. There are three different communication architectures which have been experimentally demonstrated using discrete electronic components for capacitive BCC channel for data rates between 1 kbps to 100 kbps. The architectures are based on digital baseband communication and passband communication with LC resonant mode driver. The best architecture is based on passband communication which has been demonstrated for reliable ECG measurement in the context of preventive healthcare.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering Computer Sciences
Identifiers
urn:nbn:se:liu:diva-122836 (URN)
Available from: 2015-11-26 Created: 2015-11-26 Last updated: 2018-01-10Bibliographically approved
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