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Ingelsson, Urban
Publications (10 of 28) Show all publications
Petersen, K., Nikolov, D., Ingelsson, U., Carlsson, G. & Larsson, E. (2012). An MPSoCs Demonstrator for Fault Injection and Fault Handling in an IEEE P1687 Environment. In: IEEE 17th European Test Symposimu (ETS 2012), Annecy, France, May 28-June 1, 2012. Paper presented at ETS12.
Open this publication in new window or tab >>An MPSoCs Demonstrator for Fault Injection and Fault Handling in an IEEE P1687 Environment
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2012 (English)In: IEEE 17th European Test Symposimu (ETS 2012), Annecy, France, May 28-June 1, 2012, 2012Conference paper, Oral presentation only (Refereed)
Abstract [en]

As fault handling in multi-processor system-on-chips (MPSoCs) is a major challenge, we have developed an MPSoC demonstrator that enables experimentation on fault injection and fault handling. Our MPSoC demonstrator consists of (1) an MPSoC model with a set of components (devices) each equipped with fault detection features, so called instruments, (2) an Instrument Access Infrastructure (IAI) based on IEEE P1687 that connects the instruments, (3) a Fault Indication and Propagation Infrastructure (FIPI) that propagates fault indications to system-level, (4) a Resource Manager (RM) to schedule jobs based on fault statuses, (5) an Instrument Manager (IM) connecting the IAI and the RM, and (6) a Fault Injection Manager (FIM) that inserts faults. The main goal of the demonstrator is to enable experimentation on different fault handling solutions. The novelty in this particular demonstrator is that it uses the existing test features, i.e. IEEE P1687 infrastructure, to assist fault handling. The demonstrator is implemented and a case study is performed.

National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-80008 (URN)
Conference
ETS12
Available from: 2012-08-17 Created: 2012-08-17 Last updated: 2018-01-12
Zadegan, F. G., Ingelsson, U., Carlsson, G. & Larsson, E. (2012). Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687. IEEE Design & Test of Computers, 29(2), 79-88
Open this publication in new window or tab >>Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
2012 (English)In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 29, no 2, p. 79-88Article in journal (Refereed) Published
Abstract [en]

This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE P1687 standard in an era where reuse of existing functional elements and integration of IP blocks is accelerating rapidly. It briefly discusses the deficiencies of existing 1149.1 (JTAG) and 1500 standards and demonstrates how the new standard, P1687, plugs these exposures by specifying JTAG as an off-chip to on-chip interface to the instrument access infrastructure. It provides a simple example to underscore the need for the standard and then builds on this example to show how the standard can be used for more complex situations.

Place, publisher, year, edition, pages
IEEE, 2012
Keywords
IEEE P1687, on-chip instruments, access procedures, ICL, PDL, reuse and retargeting
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-73803 (URN)10.1109/MDT.2012.2182984 (DOI)000306207100011 ()
Available from: 2012-01-13 Created: 2012-01-13 Last updated: 2018-01-12Bibliographically approved
Sengupta, B., Ingelsson, U. & Larsson, E. (2012). Scheduling Tests for 3D Stacked Chips under Power Constraints. Journal of electronic testing, 28(1), 121-135
Open this publication in new window or tab >>Scheduling Tests for 3D Stacked Chips under Power Constraints
2012 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 28, no 1, p. 121-135Article in journal (Refereed) Published
Abstract [en]

This paper addresses Test Application Time (TAT) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the TAT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in TAT.

Place, publisher, year, edition, pages
Springer Verlag (Germany), 2012
Keywords
Power constrained test scheduling, 3D integration
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-77342 (URN)10.1007/s10836-011-5244-5 (DOI)000302868800011 ()
Note
Funding Agencies|Swedish Research Council||Available from: 2012-05-11 Created: 2012-05-11 Last updated: 2017-12-07
SenGupta, B., Ingelsson, U. & Larsson, E. (2012). Test Planning for Core-based 3D Stacked ICs under Power Constraints. In: RASDAT 2012. Paper presented at 3rd IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT 2012), Hyderabad, India, January 7-8, 2012.
Open this publication in new window or tab >>Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012 (English)In: RASDAT 2012, 2012Conference paper, Oral presentation only (Refereed)
Abstract [en]

Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D SICs with two chips and 3D SICs with an arbitrary number of chips. We motivate the problem by demostrating the trade-off between test time and hardware, within a power constraint, while arriving at the minimal cost.

National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-77288 (URN)
Conference
3rd IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT 2012), Hyderabad, India, January 7-8, 2012
Available from: 2012-05-10 Created: 2012-05-10 Last updated: 2018-01-12
SenGupta, B., Ingelsson, U. & Larsson, E. (2012). Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. In: VLSI 2012: . Paper presented at 25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012. IEEE
Open this publication in new window or tab >>Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
2012 (English)In: VLSI 2012, IEEE , 2012Conference paper, Published paper (Refereed)
Abstract [en]

Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSVSICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

Place, publisher, year, edition, pages
IEEE, 2012
Series
VLSI Design, ISSN 1063-9667
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-77289 (URN)10.1109/VLSID.2012.111 (DOI)9780769546384 (ISBN)9781467304382 (ISBN)
Conference
25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012
Available from: 2012-05-10 Created: 2012-05-10 Last updated: 2018-01-12
Wang, Q., Wallin, A., Izosimov, V., Ingelsson, U. & Peng, Z. (2012). Test tool qualification through fault injection. In: Test Symposium (ETS 2012). Paper presented at 17th IEEE European Test Symposium (ETS 2012), Annecy, France, May 28-June 1, 2012. IEEE
Open this publication in new window or tab >>Test tool qualification through fault injection
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2012 (English)In: Test Symposium (ETS 2012), IEEE , 2012Conference paper, Poster (with or without abstract) (Other academic)
Abstract [en]

According to ISO 26262, a recent automotive functional safety standard, verification tools shall undergo qualification, e.g. to ensure that they do not fail to detect faults that can lead to violation of functional safety requirements. We present a semi-automatic qualification method involving a monitor and fault injection that reduce cost in the qualification process. We experiment on a verification tool implemented in LabVIEW.

Place, publisher, year, edition, pages
IEEE, 2012
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-91508 (URN)10.1109/ETS.2012.6233042 (DOI)978-1-4673-0696-6 (ISBN)e-978-1-4673-0695-9 (ISBN)
Conference
17th IEEE European Test Symposium (ETS 2012), Annecy, France, May 28-June 1, 2012
Available from: 2013-04-26 Created: 2013-04-26 Last updated: 2018-01-11
Zadegan, F. G., Ingelsson, U., Larsson, E. & Carlsson, G. (2011). A Study of Instrument Reuse and Retargeting in P1687. In: IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011.. Paper presented at WRTLT 2011.
Open this publication in new window or tab >>A Study of Instrument Reuse and Retargeting in P1687
2011 (English)In: IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011., 2011Conference paper, Oral presentation only (Refereed)
Abstract [en]

Modern chips may contain a large number of embedded test, debug, configuration, and monitoring features, called instruments. An instrument and its instrument data, instrument access procedures, may be pre-developed and reused and instruments may be accessed in different ways through the life-time of the chip, which requires retargeting. To address instruments reuse and retargeting, IEEE P1678 specifies a hardware architecture, a hardware description language, and an access procedure description language. In this paper, we investigate how P1687 facilitates instrument access procedure reuse and retargeting.

National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-79300 (URN)
Conference
WRTLT 2011
Available from: 2012-07-09 Created: 2012-07-09 Last updated: 2018-01-12
Zadegan, F. G., Ingelsson, U., Carlsson, G. & Larsson, E. (2011). Design Automation for IEEE P1687. In: Proceedings -Design, Automation and Test in Europe, DATE: . Paper presented at 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011; Grenoble; France (pp. 1-6). IEEE
Open this publication in new window or tab >>Design Automation for IEEE P1687
2011 (English)In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2011, p. 1-6Conference paper, Published paper (Refereed)
Abstract [en]

The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total access time and average access time.

Place, publisher, year, edition, pages
IEEE, 2011
Series
Design, automation and test in Europe, ISSN 1530-1591
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-63309 (URN)10.1109/DATE.2011.5763228 (DOI)978-1-61284-208-0 (ISBN)
Conference
14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011; Grenoble; France
Available from: 2010-12-15 Created: 2010-12-15 Last updated: 2014-10-22Bibliographically approved
Nikolov, D., Ingelsson, U., Singh, V. & Larsson, E. (2011). Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization. In: 5th Workshop on Dependable and Secure Nanocomputing (WSDN 2011), Hong Kong, June 27, 2011: . Paper presented at WSDN11. IEEE
Open this publication in new window or tab >>Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
2011 (English)In: 5th Workshop on Dependable and Secure Nanocomputing (WSDN 2011), Hong Kong, June 27, 2011, IEEE , 2011Conference paper, Published paper (Refereed)
Abstract [en]

Increasing soft error rates for semiconductor devices manufactured in later technologies enforces the use of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). However, RRC introduces time overhead that increases the completion (execution) time. For non-real-time systems, research have focused on optimizing RRC and shown that it is possible to find the optimal number of checkpoints such that the average execution time is minimal. While minimal average execution time is important, it is for real-time systems important to provide a high probability that deadlines are met. Hence, there is a need of probabilistic guarantees that jobs employing RRC complete before a given deadline. First, we present a mathematical framework for the evaluation of level of confidence, the probability that a given deadline is met, when RRC is employed. Second, we present an optimization method for RRC that finds the number of checkpoints that results in the minimal completion time while the minimal completion time satisfies a given level of confidence requirement. Third, we use the proposed framework to evaluate probabilistic guarantees for RRC optimization in non-real-time systems.

Place, publisher, year, edition, pages
IEEE, 2011
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-80007 (URN)10.1109/DSNW.2011.5958836 (DOI)978-1-4577-0374-4 (ISBN)
Conference
WSDN11
Available from: 2012-08-17 Created: 2012-08-17 Last updated: 2018-01-12
Ingelsson, U., Chang, S.-Y. & Larsson, E. (2011). Measurement Point Selection for In-Operation Wear-Out Monitoring. In: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011.: . Paper presented at 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011; Cottbus; Germany (pp. 381-386). IEEE
Open this publication in new window or tab >>Measurement Point Selection for In-Operation Wear-Out Monitoring
2011 (English)In: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011., IEEE , 2011, p. 381-386Conference paper, Published paper (Refereed)
Abstract [en]

In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wearout monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. The proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. The method is demonstrated on ISCAS85 benchmark ICs with encouraging results.

Place, publisher, year, edition, pages
IEEE, 2011
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-66349 (URN)10.1109/DDECS.2011.5783115 (DOI)978-1-4244-9755-3 (ISBN)
Conference
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011; Cottbus; Germany
Available from: 2011-03-11 Created: 2011-03-11 Last updated: 2018-09-11Bibliographically approved
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