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Zadegan, Farrokh Ghani
Alternative names
Publications (10 of 10) Show all publications
Zadegan, F. G., Carlsson, G. & Larsson, E. (2013). Scenario-Based Network Design for P1687. In: SSoCC'13: . Paper presented at The 12th Swedish System-on-Chip Conference (SSoCC 2013), Ystad, Sweden, May 6-7, 2013.
Open this publication in new window or tab >>Scenario-Based Network Design for P1687
2013 (English)In: SSoCC'13, 2013Conference paper, Oral presentation only (Other academic)
Abstract [en]

To improve testability of integrated circuits against manufacturing defects, and to better handle the complexity of modern designs during debugging and characterization, it is common to embed testing, debugging, configuration, and monitoring features (called on-chip instruments) within the chip. IEEE P1687 proposes a flexible network for accessing and operating such on-chip instruments from outside the chip, and facilitates reusing instrument access procedures in different usage scenarios throughout the chip's life-cycle-spanning from chip prototyping to in-field test. Efficient access (in terms of time) to on-chip instruments requires careful design of the instrument access network. However, it is shown that a network optimized for one usage scenario, is not necessarily efficient in other scenarios. To address the problem of designing a network which is efficient in terms of instrument access time under multiple scenarios, in this work, we compare a number of network design approaches provided by P1687, in terms of instrument access time and hardware overhead.

National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-92593 (URN)
Conference
The 12th Swedish System-on-Chip Conference (SSoCC 2013), Ystad, Sweden, May 6-7, 2013
Available from: 2013-05-14 Created: 2013-05-14 Last updated: 2018-01-11Bibliographically approved
Ghani Zadegan, F., Ingelsson, U., Carlsson, G. & Larsson, E. (2012). Access Time Analysis for IEEE P1687. I.E.E.E. transactions on computers (Print), 61(10), 1459-1472
Open this publication in new window or tab >>Access Time Analysis for IEEE P1687
2012 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 61, no 10, p. 1459-1472Article in journal (Refereed) Published
Abstract [en]

The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e., concurrent schedule and sequential schedule. In the analysis, two types of overhead are identified, i.e., network configuration data overhead and JTAG protocol overhead. The algorithms are implemented and employed in a parametric analysis and in experiments on realistic industrial designs.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2012
Keywords
Access time calculation, IEEE P1687 IJTAG, P1687 network architectures, instrument access schedules
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-82041 (URN)10.1109/TC.2011.155 (DOI)000307788900008 ()
Available from: 2012-10-01 Created: 2012-09-28 Last updated: 2017-12-07
Zadegan, F. G., Ingelsson, U., Carlsson, G. & Larsson, E. (2012). Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687. IEEE Design & Test of Computers, 29(2), 79-88
Open this publication in new window or tab >>Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
2012 (English)In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 29, no 2, p. 79-88Article in journal (Refereed) Published
Abstract [en]

This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE P1687 standard in an era where reuse of existing functional elements and integration of IP blocks is accelerating rapidly. It briefly discusses the deficiencies of existing 1149.1 (JTAG) and 1500 standards and demonstrates how the new standard, P1687, plugs these exposures by specifying JTAG as an off-chip to on-chip interface to the instrument access infrastructure. It provides a simple example to underscore the need for the standard and then builds on this example to show how the standard can be used for more complex situations.

Place, publisher, year, edition, pages
IEEE, 2012
Keywords
IEEE P1687, on-chip instruments, access procedures, ICL, PDL, reuse and retargeting
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-73803 (URN)10.1109/MDT.2012.2182984 (DOI)000306207100011 ()
Available from: 2012-01-13 Created: 2012-01-13 Last updated: 2018-01-12Bibliographically approved
Zadegan, F. G., Ingelsson, U., Larsson, E. & Carlsson, G. (2011). A Study of Instrument Reuse and Retargeting in P1687. In: IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011.. Paper presented at WRTLT 2011.
Open this publication in new window or tab >>A Study of Instrument Reuse and Retargeting in P1687
2011 (English)In: IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011., 2011Conference paper, Oral presentation only (Refereed)
Abstract [en]

Modern chips may contain a large number of embedded test, debug, configuration, and monitoring features, called instruments. An instrument and its instrument data, instrument access procedures, may be pre-developed and reused and instruments may be accessed in different ways through the life-time of the chip, which requires retargeting. To address instruments reuse and retargeting, IEEE P1678 specifies a hardware architecture, a hardware description language, and an access procedure description language. In this paper, we investigate how P1687 facilitates instrument access procedure reuse and retargeting.

National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-79300 (URN)
Conference
WRTLT 2011
Available from: 2012-07-09 Created: 2012-07-09 Last updated: 2018-01-12
Zadegan, F. G., Ingelsson, U., Carlsson, G. & Larsson, E. (2011). Automated Design for IEEE P1687. In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011.. Paper presented at SSoCC 2011.
Open this publication in new window or tab >>Automated Design for IEEE P1687
2011 (English)In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011., 2011Conference paper, Oral presentation only (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-70307 (URN)
Conference
SSoCC 2011
Available from: 2011-09-01 Created: 2011-09-01 Last updated: 2013-05-13
Zadegan, F. G., Ingelsson, U., Carlsson, G. & Larsson, E. (2011). Design Automation for IEEE P1687. In: Proceedings -Design, Automation and Test in Europe, DATE: . Paper presented at 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011; Grenoble; France (pp. 1-6). IEEE
Open this publication in new window or tab >>Design Automation for IEEE P1687
2011 (English)In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2011, p. 1-6Conference paper, Published paper (Refereed)
Abstract [en]

The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total access time and average access time.

Place, publisher, year, edition, pages
IEEE, 2011
Series
Design, automation and test in Europe, ISSN 1530-1591
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-63309 (URN)10.1109/DATE.2011.5763228 (DOI)978-1-61284-208-0 (ISBN)
Conference
14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011; Grenoble; France
Available from: 2010-12-15 Created: 2010-12-15 Last updated: 2014-10-22Bibliographically approved
Zadegan, F. G., Ingelsson, U., Asani, G., Carlsson, G. & Larsson, E. (2011). Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints. In: Proceedings of the Asian Test Symposium: . Paper presented at 20th Asian Test Symposium, ATS 2011; New Delhi; India (pp. 525-531). IEEE
Open this publication in new window or tab >>Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
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2011 (English)In: Proceedings of the Asian Test Symposium, IEEE , 2011, p. 525-531Conference paper, Published paper (Refereed)
Abstract [en]

In contrast to IEEE 1149.1, IEEE P1687 allows, through segment insertion bits, flexible scan paths for accessing on-chip instruments, such as test, debug, monitoring, measurement and configuration features. Flexible access to embedded instruments allows test time reduction, which is important at production test. However, the test access scheme should be carefully selected such that resource constraints are not violated and power constraints are met. For IEEE P1687, we detail in this paper session-based and session-less test scheduling, and propose resource and power-aware test scheduling algorithms for the detailed scheduling types. Results using the implementation of our algorithms shows on ITC’02-based benchmarks significant test time reductions when compared to non-optimized test schedules.

Place, publisher, year, edition, pages
IEEE, 2011
Series
Proceedings of the Asian Test Symposium, ISSN 1081-7735
National Category
Engineering and Technology Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-70033 (URN)10.1109/ATS.2011.80 (DOI)978-1-4577-1984-4 (ISBN)
Conference
20th Asian Test Symposium, ATS 2011; New Delhi; India
Available from: 2011-08-15 Created: 2011-08-15 Last updated: 2014-10-16
Asani, G., Zadegan, F. G., Ingelsson, U., Carlsson, G. & Larsson, E. (2011). Test Scheduling with Constraints for IEEE P1687 (poster). In: International Test Conference (ITC11), Anaheim, CA, USA, September 18-23, 2011.. Paper presented at ITC 2011.
Open this publication in new window or tab >>Test Scheduling with Constraints for IEEE P1687 (poster)
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2011 (English)In: International Test Conference (ITC11), Anaheim, CA, USA, September 18-23, 2011., 2011Conference paper, Poster (with or without abstract) (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-70034 (URN)
Conference
ITC 2011
Available from: 2011-08-15 Created: 2011-08-15 Last updated: 2013-05-13
Larsson, E., Zadegan, F. G., Ingelsson, U. & Carlsson, G. (2010). Test scheduling on IJTAG. In: Nordic Test Forum (NTF 2010), Drammen, Norway.. Paper presented at NTF 2010.
Open this publication in new window or tab >>Test scheduling on IJTAG
2010 (English)In: Nordic Test Forum (NTF 2010), Drammen, Norway., 2010Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-63310 (URN)
Conference
NTF 2010
Available from: 2010-12-15 Created: 2010-12-15 Last updated: 2010-12-21Bibliographically approved
Zadegan, F. G., Ingelsson, U., Carlsson, G. & Larsson, E. (2010). Test Time Analysis for IEEE P1687. In: Proceedings of the Asian Test Symposium: . Paper presented at 2010 19th IEEE Asian Test Symposium, ATS 2010; Shanghai; China (pp. 455-460).
Open this publication in new window or tab >>Test Time Analysis for IEEE P1687
2010 (English)In: Proceedings of the Asian Test Symposium, 2010, p. 455-460Conference paper, Published paper (Refereed)
Abstract [en]

The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-59597 (URN)10.1109/ATS.2010.83 (DOI)9780769542485 (ISBN)
Conference
2010 19th IEEE Asian Test Symposium, ATS 2010; Shanghai; China
Available from: 2010-09-21 Created: 2010-09-21 Last updated: 2017-02-14Bibliographically approved
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