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BETA
SenGupta, Breeta
Alternative names
Publications (10 of 10) Show all publications
Sengupta, B., Ingelsson, U. & Larsson, E. (2012). Scheduling Tests for 3D Stacked Chips under Power Constraints. Journal of electronic testing, 28(1), 121-135
Open this publication in new window or tab >>Scheduling Tests for 3D Stacked Chips under Power Constraints
2012 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 28, no 1, p. 121-135Article in journal (Refereed) Published
Abstract [en]

This paper addresses Test Application Time (TAT) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the TAT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in TAT.

Place, publisher, year, edition, pages
Springer Verlag (Germany), 2012
Keywords
Power constrained test scheduling, 3D integration
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-77342 (URN)10.1007/s10836-011-5244-5 (DOI)000302868800011 ()
Note
Funding Agencies|Swedish Research Council||Available from: 2012-05-11 Created: 2012-05-11 Last updated: 2017-12-07
SenGupta, B., Ingelsson, U. & Larsson, E. (2012). Test Planning for Core-based 3D Stacked ICs under Power Constraints. In: RASDAT 2012. Paper presented at 3rd IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT 2012), Hyderabad, India, January 7-8, 2012.
Open this publication in new window or tab >>Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012 (English)In: RASDAT 2012, 2012Conference paper, Oral presentation only (Refereed)
Abstract [en]

Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D SICs with two chips and 3D SICs with an arbitrary number of chips. We motivate the problem by demostrating the trade-off between test time and hardware, within a power constraint, while arriving at the minimal cost.

National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-77288 (URN)
Conference
3rd IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT 2012), Hyderabad, India, January 7-8, 2012
Available from: 2012-05-10 Created: 2012-05-10 Last updated: 2018-01-12
SenGupta, B., Ingelsson, U. & Larsson, E. (2012). Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. In: VLSI 2012: . Paper presented at 25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012. IEEE
Open this publication in new window or tab >>Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
2012 (English)In: VLSI 2012, IEEE , 2012Conference paper, Published paper (Refereed)
Abstract [en]

Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSVSICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

Place, publisher, year, edition, pages
IEEE, 2012
Series
VLSI Design, ISSN 1063-9667
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-77289 (URN)10.1109/VLSID.2012.111 (DOI)9780769546384 (ISBN)9781467304382 (ISBN)
Conference
25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012
Available from: 2012-05-10 Created: 2012-05-10 Last updated: 2018-01-12
SenGupta, B., Ingelsson, U. & Larsson, E. (2011). Scheduling Tests for 3D Stacked Chips under Power Constraints. In: Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011, Queenstown, NZ. Paper presented at Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011, Queenstown, NZ (pp. 72-77). Washington, DC, USA: IEEE Computer Society
Open this publication in new window or tab >>Scheduling Tests for 3D Stacked Chips under Power Constraints
2011 (English)In: Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011, Queenstown, NZ, Washington, DC, USA: IEEE Computer Society , 2011, p. 72-77Conference paper, Published paper (Refereed)
Abstract [en]

This paper addresses Test Application Time (TAT)reduction for core-based 3D Stacked ICs (SICs). Applyingtraditional test scheduling methods used for non-stacked chiptesting where the same test schedule is applied both at wafer testand at final test to SICs, leads to unnecessarily high TAT. This isbecause the final test of 3D-SICs includes the testing of all thestacked chips. A key challenge in 3D-SIC testing is to reduce TATby co-optimizing the wafer test and the final test while meetingpower constraints. We consider a system of chips with coresequipped with dedicated Built-In-Self-Test (BIST)-engines andpropose a test scheduling approach to reduce TAT while meetingthe power constraints. Depending on the test schedule, the controllines that are required for BIST can be shared among severalBIST engines. This is taken into account in the test schedulingapproach and experiments show significant savings in TAT.

Place, publisher, year, edition, pages
Washington, DC, USA: IEEE Computer Society, 2011
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-70035 (URN)10.1109/DELTA.2011.23 (DOI)978-1-4244-9357-9 (ISBN)
Conference
Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011, Queenstown, NZ
Available from: 2011-08-15 Created: 2011-08-15 Last updated: 2013-05-13
SenGupta, B., Ingelsson, U. & Larsson, E. (2011). Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias. In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011. Paper presented at SSoCC'11.
Open this publication in new window or tab >>Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011 (English)In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011, 2011Conference paper, Published paper (Other academic)
Abstract [en]

In this paper we have proposed a test cost model for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike in the case of non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the most cost-efficient test flow for 3D TSV-SICs is yet undefined. Therefore, analysing the various alternatives of test flow, we present a cost model with the optimal test flow. In the test flow alternatives, we analyse the effect of all possible moments of testing for a 3D TSV-SIC, viz., wafer sort, intermediate test and package test. For the optimal test flow, we have performed experiments with various varying yield and test time parameters, which further support our claim.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-69731 (URN)
Conference
SSoCC'11
Available from: 2011-08-01 Created: 2011-08-01 Last updated: 2013-05-13
SenGupta, B., Ingelsson, U. & Larsson, E. (2011). Test Planning for 3D Stacked ICs with Through-Silicon Vias. In: 3D-TEST. Paper presented at 2nd IEEE Intl. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Anaheim, CA, USA, September 22-23, 2011.
Open this publication in new window or tab >>Test Planning for 3D Stacked ICs with Through-Silicon Vias
2011 (English)In: 3D-TEST, 2011Conference paper, Published paper (Refereed)
Abstract [en]

Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs and 3D TSV-SICs with two chips in the stack. We have implemented our techniques and experiments show significant reduction of test cost.

National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-77287 (URN)
Conference
2nd IEEE Intl. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Anaheim, CA, USA, September 22-23, 2011
Available from: 2012-05-10 Created: 2012-05-10 Last updated: 2018-01-12
SenGupta, B., Ingelsson, U. & Larsson, E. (2011). Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias (poster). In: European Test Symposium (ETS11), Trondheim, Norway, May 23-27, 2011.. Paper presented at ETS'11.
Open this publication in new window or tab >>Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias (poster)
2011 (English)In: European Test Symposium (ETS11), Trondheim, Norway, May 23-27, 2011., 2011Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-69732 (URN)
Conference
ETS'11
Available from: 2011-08-01 Created: 2011-08-01 Last updated: 2013-05-13
SenGupta, B., Ingelsson, U. & Larsson, E. (2011). Test Scheduling for 3D Stacked ICs under Power Constraints. In: 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011.
Open this publication in new window or tab >>Test Scheduling for 3D Stacked ICs under Power Constraints
2011 (English)In: 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011, 2011Conference paper, Published paper (Refereed)
Abstract [en]

This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.

National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-65885 (URN)
Available from: 2011-02-23 Created: 2011-02-23 Last updated: 2018-01-12
SenGupta, B., Ingelsson, U. & Larsson, E. (2010). Power Constrained Test Scheduling for 3D Stacked Chips: (poster). In: 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA.: . Paper presented at 3DTEST 2010.
Open this publication in new window or tab >>Power Constrained Test Scheduling for 3D Stacked Chips: (poster)
2010 (English)In: 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA., 2010Conference paper, Poster (with or without abstract) (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-63308 (URN)
Conference
3DTEST 2010
Available from: 2010-12-15 Created: 2010-12-15 Last updated: 2017-03-20
SenGupta, B., Ingelsson, U. & Larsson, E. (2010). Scheduling Tests for Stacked 3D Chips under Power Constraints. In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed).
Open this publication in new window or tab >>Scheduling Tests for Stacked 3D Chips under Power Constraints
2010 (English)In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-59602 (URN)
Available from: 2010-09-21 Created: 2010-09-21 Last updated: 2010-09-28
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