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Aghaee Ghaleshahi, NimaORCID iD iconorcid.org/0000-0002-8138-8443
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Publications (10 of 14) Show all publications
Aghaee, N., Peng, Z. & Eles, P. (2015). A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs. Journal of electronic testing, 31(5), 503-523
Open this publication in new window or tab >>A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs
2015 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, ISSN 0923-8174, Vol. 31, no 5, p. 503-523Article in journal (Refereed) Published
Abstract [en]

n a modern three-dimensional integrated circuit (3D IC), vertically stacked dies are interconnected using through silicon vias. 3D ICs are subject to undesirable temperature-cycling phenomena such as through silicon via protrusion as well as void formation and growth. These cycling effects that occur during early life result in opens, resistive opens, and stress induced carrier mobility reduction. Consequently these early-life failures lead to products that fail shortly after the start of their use. Artificially-accelerated temperature cycling, before the manufacturing test, helps to detect such early-life failures that are otherwise undetectable. A test-ordering based temperature-cycling acceleration technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration methods. All these result in a reduction in the overall test costs. The proposed method is a test-ordering and schedule based solution that enforces the required temperature cycling effect and simultaneously performs the tests whenever appropriate. Experimental results demonstrate the efficiency of the proposed technique.

Keywords
Temperature cycling test, Test scheduling, Test ordering, 3D stacked IC
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-123489 (URN)10.1007/s10836-015-5541-5 (DOI)000366640800007 ()
Available from: 2015-12-18 Created: 2015-12-18 Last updated: 2018-01-10
Aghaee Ghaleshahi, N., Peng, Z. & Eles, P. (2015). An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs. In: 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, Jan. 19-22, 2015.: . Paper presented at ASP-DAC 2015 (pp. 526-531). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs
2015 (English)In: 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, Jan. 19-22, 2015., Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 526-531Conference paper, Published paper (Refereed)
Abstract [en]

In a modern 3D IC, electrical connections between vertically stacked dies are made using through silicon vias. Through silicon vias are subject to undesirable early-life effects such as protrusion as well as void formation and growth. These effects result in opens, resistive opens, and stress induced carrier mobility reduction, and consequently circuit failures. Operating the ICs under extreme temperature cycling can effectively accelerate such early-life failures and make them detectable at the manufacturing test process. An integrated temperature-cycling acceleration and test technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration procedures. All these result in a reduction in the overall test costs. The proposed method is a schedule-based solution that creates the required temperature cycling effect along with performing the tests. Experimental results demonstrate its efficiency.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-116878 (URN)10.1109/ASPDAC.2015.7059060 (DOI)000380442800103 ()978-1-4799-7792-5 (ISBN)
Conference
ASP-DAC 2015
Available from: 2015-04-08 Created: 2015-04-08 Last updated: 2016-09-19
Aghaee Ghaleshahi, N., Peng, Z. & Eles, P. (2015). Efficient Test Application for Rapid Multi-Temperature Testing. In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI: . Paper presented at Great Lakes Symposium on VLSI, Pittsburgh, Pennsylvania, USA, May 20-22, 2015 (pp. 3-8). Association for Computing Machinery (ACM)
Open this publication in new window or tab >>Efficient Test Application for Rapid Multi-Temperature Testing
2015 (English)In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI, Association for Computing Machinery (ACM), 2015, p. 3-8Conference paper, Published paper (Other academic)
Abstract [en]

Different defects may manifest themselves at different temperatures. Therefore, the tests that target such temperature-dependent defects must be applied at different temperatures appropriate for detecting them. Such multi-temperature testing scheme applies tests at different required temperatures. It is known that a test's power dissipation depends on the previously applied test. Therefore, the same set of tests when organized differently dissipates different amounts of power. The technique proposed in this paper organizes the tests efficiently so that the resulted power levels lead to the required temperatures. Consequently a rapid multi-temperature testing is achieved. Experimental studies demonstrate the efficiency of the proposed technique.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2015
Keywords
Temperature-dependent defects, multi-temperature testing, temperature simulation, test ordering, test scheduling, 3D stacked IC (3D-SIC)
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-129003 (URN)10.1145/2742060.2742064 (DOI)978-1-4503-3474-7 (ISBN)
Conference
Great Lakes Symposium on VLSI, Pittsburgh, Pennsylvania, USA, May 20-22, 2015
Available from: 2016-06-08 Created: 2016-06-08 Last updated: 2018-01-10Bibliographically approved
Aghaee, N., Peng, Z. & Eles, P. (2015). Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 23(12), 2992-3005
Open this publication in new window or tab >>Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs
2015 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 23, no 12, p. 2992-3005Article in journal (Refereed) Published
Abstract [en]

Large temperature gradients exacerbate various types of defects including early-life failures and delay faults. Efficient detection of these defects requires that burn-in and test for delay faults, respectively, are performed when temperature gradients with proper magnitudes are enforced on an Integrated Circuit (IC). This issue is much more important for 3-D stacked ICs (3-D SICs) compared with 2-D ICs because of the larger temperature gradients in 3-D SICs. In this paper, two methods to efficiently enforce the specified temperature gradients on the IC, for burn-in and delay-fault test, are proposed. The specified temperature gradients are enforced by applying high-power stimuli to the cores of the IC under test through the test access mechanism. Therefore, no external heating mechanism is required. The tests, high power stimuli, and cooling intervals are scheduled together based on temperature simulations so that the desired temperature gradients are rapidly enforced. The schedule generation is guided by functions derived from a set of thermal equations. The experimental results demonstrate the efficiency of the proposed methods.

Keywords
3-D stacked IC (3-D SIC) test, burn-in, temperature gradients, test scheduling, test scheduling
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-123487 (URN)10.1109/TVLSI.2014.2380477 (DOI)000365206300022 ()
Available from: 2015-12-18 Created: 2015-12-18 Last updated: 2018-01-10
Aghaee Ghaleshahi, N. (2015). Thermal Issues in Testing of Advanced Systems on Chip. (Doctoral dissertation). Linkoping University: Linköping University Electronic Press
Open this publication in new window or tab >>Thermal Issues in Testing of Advanced Systems on Chip
2015 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.

Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.

Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced.

The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.

All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.

Place, publisher, year, edition, pages
Linkoping University: Linköping University Electronic Press, 2015. p. 197
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1702
Keywords
SoC test, test scheduling, Adaptive test, Temperature awareness, Process variation, Thermal simulation, 3D stacked IC (3DSIC) test, Burn-in, Temperature gradients, Temperature Cycling Test, Test Ordering
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-120798 (URN)10.3384/diss.diva-120798 (DOI)978-91-7685-949-0 (ISBN)
Public defence
2015-10-23, Visionen, Hus B, Campus Valla, Linköping, 13:15 (English)
Opponent
Supervisors
Funder
CUGS (National Graduate School in Computer Science), 1053-220800
Available from: 2015-09-23 Created: 2015-08-25 Last updated: 2015-09-24Bibliographically approved
Aghaee Ghaleshahi, N., Peng, Z. & Eles, P. (2014). An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014: . Paper presented at Design, Automation and Test in Europe Conference and Exhibition (DATE 2014), Dresden, Germany, March 24-28, 2014. IEEE conference proceedings
Open this publication in new window or tab >>An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs
2014 (English)In: Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, IEEE conference proceedings, 2014Conference paper, Published paper (Refereed)
Abstract [en]

Burn-in is usually carried out with high temperature and elevated voltage. Since some of the early-life failures depend not only on high temperature but also on temperature gradients, simply raising up the temperature of an IC is not sufficient to detect them. This is especially true for 3D stacked ICs, since they have usually very large temperature gradients. The efficient detection of these early-life failures requires that specific temperature gradients are enforced as a part of the burn-in process. This paper presents an efficient method to do so by applying high power stimuli to the cores of the IC under burn-in through the test access mechanism. Therefore, no external heating equipment is required. The scheduling of the heating and cooling intervals to achieve the required temperature gradients is based on thermal simulations and is guided by functions derived from a set of thermal equations. Experimental results demonstrate the efficiency of the proposed method.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2014
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-106738 (URN)10.7873/DATE2014.142 (DOI)000354965500129 ()978-3-9815370-2-4 (ISBN)
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE 2014), Dresden, Germany, March 24-28, 2014
Available from: 2014-05-20 Created: 2014-05-20 Last updated: 2018-01-11
Aghaee Ghaleshahi, N., Peng, Z. & Eles, P. (2014). Process-Variation Aware Multi-temperature Test Scheduling. In: 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems: . Paper presented at 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014 (pp. 32-37). IEEE conference proceedings
Open this publication in new window or tab >>Process-Variation Aware Multi-temperature Test Scheduling
2014 (English)In: 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems, IEEE conference proceedings, 2014, p. 32-37Conference paper, Published paper (Refereed)
Abstract [en]

Chips manufactured with deep sub micron technologies are prone to large process variation and temperature-dependent defects. In order to provide high test efficiency, the tests for temperature-dependent defects should be applied at appropriate temperature ranges. Existing static scheduling techniques achieve these specified temperatures by scheduling the tests, specially developed heating sequences, and cooling intervals together. Because of the temperature uncertainty induced by process variation, a static test schedule is not capable of applying the tests at intended temperatures in an efficient manner. As a result the test cost will be very high. In this paper, an adaptive test scheduling method is introduced that utilizes on-chip temperature sensors in order to adapt the test schedule to the actual temperatures. The proposed method generates a low cost schedule tree based on the variation statistics and thermal simulations in the design phase. During the test, a chip selects an appropriate schedule dynamically based on temperature sensor readings. A 23% decrease in the likelihood that tests are not applied at the intended temperatures is observed in the experimental studies in addition to 20% reduction in test application time.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2014
Series
International Conference on VLSI Design. Proceedings, ISSN 1063-9667
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-106739 (URN)10.1109/VLSID.2014.13 (DOI)000350732700015 ()2-s2.0-84894553976 (Scopus ID)
Conference
27th International Conference on VLSI Design and 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014
Available from: 2014-05-20 Created: 2014-05-20 Last updated: 2018-01-11Bibliographically approved
Aghaee Ghaleshahi, N., Peng, Z. & Eles, P. (2013). Process-variation and Temperature Aware SoC Test Scheduling Technique. Journal of electronic testing, 29(4), 499-520
Open this publication in new window or tab >>Process-variation and Temperature Aware SoC Test Scheduling Technique
2013 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 29, no 4, p. 499-520Article in journal (Refereed) Published
Abstract [en]

High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC'02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.

Place, publisher, year, edition, pages
Springer, 2013
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-89972 (URN)10.1007/s10836-013-5374-z (DOI)000324106100005 ()
Available from: 2013-03-12 Created: 2013-03-12 Last updated: 2018-01-11Bibliographically approved
Aghaee Ghaleshahi, N., Peng, Z. & Eles, P. (2013). Temperature-Gradient Based Burn-In for 3D Stacked ICs. In: The 12th Swedish System-on-Chip Conference (SSoCC 2013), Ystad, Sweden, May 6-7, 2013 (not reviewed, not printed).: . Paper presented at SSoCC'13.
Open this publication in new window or tab >>Temperature-Gradient Based Burn-In for 3D Stacked ICs
2013 (English)In: The 12th Swedish System-on-Chip Conference (SSoCC 2013), Ystad, Sweden, May 6-7, 2013 (not reviewed, not printed)., 2013Conference paper, Oral presentation only (Other academic)
Abstract [en]

3D Stacked IC fabrication, using Through-Silicon-Vias, is a promising technology for future integrated circuits. However, large temperature gradients may exacerbate early-life-failures to the extent that the commercialization of 3D Stacked ICs is challenged. The effective detection of these early-life-failures requires that burn-in is performed when the IC’s temperatures comply with the thermal maps that properly specify the temperature gradients. In this paper, two methods that efficiently generate and maintain the specified thermal maps are proposed. The thermal maps are achieved by applying heating and cooling intervals to the chips under test through test access mechanisms. Therefore, no external heating system is required. The scheduling of the heating and cooling intervals is based on thermal simulations. The schedule generation is guided by functions that are derived from the temperature equations. Experimental results demonstrate the efficiency of the proposed method.

National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-92594 (URN)
Conference
SSoCC'13
Available from: 2013-05-14 Created: 2013-05-14 Last updated: 2018-01-11
Aghaee Ghaleshahi, N., Peng, Z. & Eles, P. (2013). Temperature-Gradient Based Test Scheduling for 3D Stacked ICs. In: 2013 IEEE International Conference on Electronics, Circuits, and Systems: . Paper presented at 20th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2013), Abu Dhabi, United Arab Emirates, December 9-12, 2013 (pp. 405-408). IEEE conference proceedings
Open this publication in new window or tab >>Temperature-Gradient Based Test Scheduling for 3D Stacked ICs
2013 (English)In: 2013 IEEE International Conference on Electronics, Circuits, and Systems, IEEE conference proceedings, 2013, p. 405-408Conference paper, Published paper (Refereed)
Abstract [en]

Defects that are dependent on temperature-gradients (e.g., delay-faults) introduce a challenge for achieving an effective test process, in particular for 3D ICs. Testing for such defects must be performed when the proper temperature gradients are enforced on the IC, otherwise these defects may escape the test. In this paper, a technique that efficiently heats up the IC during test so that it complies with the specified temperature gradients is proposed. The specified temperature gradients are achieved by applying heating sequences to the cores of the IC under test trough test access mechanism; thus no external heating mechanism is required. The scheduling of the test and heating sequences is based on thermal simulations. The schedule generation is guided by functions derived from the IC's temperature equation. Experimental results demonstrate that the proposed technique offers considerable test time savings.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2013
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-106740 (URN)10.1109/ICECS.2013.6815440 (DOI)000339725900110 ()978-1-4799-2452-3 (ISBN)
Conference
20th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2013), Abu Dhabi, United Arab Emirates, December 9-12, 2013
Available from: 2014-05-20 Created: 2014-05-20 Last updated: 2018-01-11Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-8138-8443

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