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Zhang, Dai
Publications (10 of 10) Show all publications
Zhang, D. & Alvandpour, A. (2016). A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS. IEEE Transactions on Circuits and Systems - II - Express Briefs, 63(3), 244-248
Open this publication in new window or tab >>A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS
2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 3, p. 244-248Article in journal (Refereed) Published
Abstract [en]

This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2016
Keyword
Digital error correction; nonbinary-weighted; redundancy; successive approximation register (SAR) analog-to-digital converter (ADC); successive approximation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-127444 (URN)10.1109/TCSII.2015.2482618 (DOI)000373136200004 ()
Available from: 2016-04-30 Created: 2016-04-26 Last updated: 2017-11-30
Zhang, D. & Alvandpour, A. (2014). Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs. IEEE Transactions on Circuits and Systems - II - Express Briefs, 61(9), 666-670
Open this publication in new window or tab >>Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs
2014 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 9, p. 666-670Article in journal (Refereed) Published
Abstract [en]

This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successive-approximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity, a bottom-up weight calibration technique accounting for noise and offset errors is proposed, and its effectiveness is demonstrated. This calibration approach can be easily incorporated into a charge-redistribution converter without modifying its main architecture and conversion sequence.

Place, publisher, year, edition, pages
IEEE, 2014
Keyword
Capacitor variation; digital error correction; nonbinary weighted; redundancy; successive approximation; successive approximation register (SAR) analog-to-digital converters (ADCs); weight calibration
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-110385 (URN)10.1109/TCSII.2014.2331111 (DOI)000341985600006 ()
Available from: 2014-09-10 Created: 2014-09-10 Last updated: 2017-12-05Bibliographically approved
Zhang, D. (2014). Ultra-Low-Power Analog-to-Digital Converters for Medical Applications. (Doctoral dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Ultra-Low-Power Analog-to-Digital Converters for Medical Applications
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultralow- power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successiveapproximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs.

The power consumption of SAR ADC is analyzed and its lower bounds are formulated. At low resolution, power is bounded by minimum feature sizes; while at medium to high resolution, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors.

Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13μm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitarray capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-VT design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB  with 1.98-μW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binary-weighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. p. 114
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1611
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-110387 (URN)10.3384/diss.diva-110387 (DOI)978-91-7519-264-2 (ISBN)
Public defence
2014-10-03, Visionen, hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2014-09-10 Created: 2014-09-10 Last updated: 2014-10-21Bibliographically approved
Zhang, D. & Alvandpour, A. (2012). A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s. In: ESSCIRC, 2012: . Paper presented at IEEE European Solid-State Circuits Conference (ESSCIRC 2012), 17-21 September 2012, Bordeaux, France (pp. 369-372). Institute of Electrical and Electronics Engineers
Open this publication in new window or tab >>A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s
2012 (English)In: ESSCIRC, 2012, Institute of Electrical and Electronics Engineers , 2012, p. 369-372Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers, 2012
Series
IEEEESSCIRC Proceedings, ISSN 1930-8833
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-86346 (URN)10.1109/ESSCIRC.2012.6341331 (DOI)978-1-4673-2211-9 (ISBN)978-1-4673-2212-6 (ISBN)
Conference
IEEE European Solid-State Circuits Conference (ESSCIRC 2012), 17-21 September 2012, Bordeaux, France
Available from: 2012-12-13 Created: 2012-12-13 Last updated: 2014-09-10
Zhang, D., Bhide, A. & Alvandpour, A. (2012). A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices. IEEE Journal of Solid-State Circuits, 47(7), 1585-1593
Open this publication in new window or tab >>A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices
2012 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 7, p. 1585-1593Article in journal (Refereed) Published
Abstract [en]

This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch boot-strapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-mu m CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2012
Keyword
ADC, analog-to-digital conversion, leakage power consumption, low-power electronics, medical implant devices, successive approximation
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-80792 (URN)10.1109/JSSC.2012.2191209 (DOI)000306913500008 ()
Available from: 2012-08-30 Created: 2012-08-30 Last updated: 2017-12-07Bibliographically approved
Zhang, D. (2012). Design of Ultra-Low-Power Analog-to-Digital Converters. (Licentiate dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Design of Ultra-Low-Power Analog-to-Digital Converters
2012 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices.

Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch. 

Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2012. p. 73
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1548
Keyword
analog-to-digital converter, ADC, successive approximation register, SAR, SAR ADC, ultra-low-power, power consumption bounds, medical implant devices
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-79276 (URN)978-91-7519-820-0 (ISBN)
Presentation
2012-09-12, Signalen, House B, Campus Valla, Linköpings universitet, Sweden, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2012-08-28 Created: 2012-07-06 Last updated: 2012-08-28Bibliographically approved
Zhang, D., Bhide, A. & Alvandpour, A. (2011). A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-um CMOS for medical implant devices. In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC). Paper presented at ESSCIRC (pp. 467-470). Helsinki, Finland: IEEE Solid-State Circuits Society
Open this publication in new window or tab >>A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-um CMOS for medical implant devices
2011 (English)In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), Helsinki, Finland: IEEE Solid-State Circuits Society, 2011, p. 467-470Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes an ultra-low-power SAR ADC in 0.13-um CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques, and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply scheme allows the SAR logic to operate at 400mV. The ADC has been fabricated in 0.13-um CMOS. In 1.0-V single-supply mode, the ADC consumes 65nW at a sampling rate of 1kS/s, while in dual-supply mode (1.0V for analog and 0.4V for digital) it consumes 53nW (18% reduction) and achieves the same ENOB of 9.12. 24% of the 53-nW total power is due to leakage. To the authors' best knowledge, this is the lowest reported power consumption of a 10-bit ADC for such sampling rates.

Place, publisher, year, edition, pages
Helsinki, Finland: IEEE Solid-State Circuits Society, 2011
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-73016 (URN)10.1109/ESSCIRC.2011.6045008 (DOI)
Conference
ESSCIRC
Available from: 2011-12-14 Created: 2011-12-14 Last updated: 2014-09-10
Zhang, D., Svensson, C. & Alvandpour, A. (2011). Power Analysis of Charge-Redistribution SAR ADCs. In: Swedish System-on-Chip Conference (SSOCC). Paper presented at SSoCC. Varberg, Sweden: IEEE Solid-State Circuits Society
Open this publication in new window or tab >>Power Analysis of Charge-Redistribution SAR ADCs
2011 (English)In: Swedish System-on-Chip Conference (SSOCC), Varberg, Sweden: IEEE Solid-State Circuits Society, 2011Conference paper, Published paper (Other academic)
Place, publisher, year, edition, pages
Varberg, Sweden: IEEE Solid-State Circuits Society, 2011
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-73045 (URN)
Conference
SSoCC
Available from: 2011-12-14 Created: 2011-12-14 Last updated: 2011-12-22
Zhang, D., Svensson, C. & Alvandpour, A. (2011). Power Consumption Bounds for SAR ADCs. In: European Conference on Circuit Theory and Design (ECCTD): . Paper presented at 20th European Conference on Circuit Theory and Design, Linköping, 29-31 Aug. 2011 (pp. 556-559). Linköping, Sweden: IEEE conference proceedings
Open this publication in new window or tab >>Power Consumption Bounds for SAR ADCs
2011 (English)In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 556-559Conference paper, Published paper (Refereed)
Abstract [en]

Power consumption is an important limitation to analog-to-digital converters. The objective of this paper is to estimate a lower bound to the power consumption of successive approximation analog-to-digital converters. This is an extension of our previous work which was limited to pipelined and flash architectures. We find that the power consumption in our case is bounded by capacitor mismatch or thermal noise at high resolution and by digital switching power at low resolution. We also evaluate our methods and the estimated lower bound is compatible with experimental data.

Place, publisher, year, edition, pages
Linköping, Sweden: IEEE conference proceedings, 2011
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-73030 (URN)10.1109/ECCTD.2011.6043594 (DOI)978-1-4577-0617-2 (ISBN)978-1-4577-0616-5 (ISBN)
Conference
20th European Conference on Circuit Theory and Design, Linköping, 29-31 Aug. 2011
Available from: 2011-12-14 Created: 2011-12-14 Last updated: 2014-09-10Bibliographically approved
Zhang, D., Bhide, A. & Alvandpour, A. (2010). Design of CMOS sampling switch for ultra-low power ADCs in biomedical applications. In: NORCHIP 2014: . Paper presented at The 32nd Norchip Conference 27-28 October 2014, Tampere, Finland (pp. 1-4). Tampere: IEEE
Open this publication in new window or tab >>Design of CMOS sampling switch for ultra-low power ADCs in biomedical applications
2010 (English)In: NORCHIP 2014, Tampere: IEEE , 2010, p. 1-4Conference paper, Published paper (Refereed)
Abstract [en]

This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakage-reduction has been designed for a 10-bit 1-kS/s successive approximation (SA) ADC in a standard 130 nm CMOS process. Post-layout simulation shows that the ADC with the proposed switch offers an effective number of bits (ENOB) of 9.5 while consuming only 64 nW.

Place, publisher, year, edition, pages
Tampere: IEEE, 2010
Keyword
CMOS integrated circuits, analogue-digital conversion, biomedical electronics, switches
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-65477 (URN)10.1109/NORCHIP.2010.5669444 (DOI)978-1-4244-8971-8 (ISBN)978-1-4244-8972-5 (ISBN)
Conference
The 32nd Norchip Conference 27-28 October 2014, Tampere, Finland
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2014-09-10Bibliographically approved
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