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Aamir, Syed Ahmed
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Publications (3 of 3) Show all publications
Ahmed Aamir, S., Harikumar, P. & Wikner, J. J. (2013). Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers. In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013: . Paper presented at IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China (pp. 381-384). IEEE conference proceedings
Open this publication in new window or tab >>Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
2013 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE conference proceedings, 2013, p. 381-384Conference paper, Oral presentation only (Refereed)
Abstract [en]

This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2013
Series
International Symposium on Circuits and Systems (ISCAS), ISSN 0271-4302 ; 2013
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-87996 (URN)10.1109/ISCAS.2013.6571860 (DOI)000332006800094 ()978-1-4673-5760-9 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
Available from: 2013-01-28 Created: 2013-01-28 Last updated: 2018-11-08
Aamir, S. A. & Wikner, J. J. (2010). A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS. In: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems: . Paper presented at 17th IEEE International Conference on Electronics, Circuits, and Systems, December 12-15, Athens, Greece (pp. 29-32). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS
2010 (English)In: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems, Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 29-32Conference paper, Published paper (Refereed)
Abstract [en]

In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inher­ent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inher­ent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit de­vices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2010
Keywords
Operational transconductance amplifiers, differential amplifiers, feedforward amplifiers, CMOS analog integrated circuits.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70358 (URN)10.1109/ICECS.2010.5724446 (DOI)
Conference
17th IEEE International Conference on Electronics, Circuits, and Systems, December 12-15, Athens, Greece
Available from: 2011-09-02 Created: 2011-09-02 Last updated: 2018-11-08Bibliographically approved
Aamir, S. A. & Wikner, J. J. (2010). A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS. In: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10. Paper presented at NORCHIP'10, 15-16 November 2010,Tampere, Finland (pp. 1-4). Tampere: www.ieee.org
Open this publication in new window or tab >>A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS
2010 (English)In: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10, Tampere: www.ieee.org , 2010, p. 1-4Conference paper, Published paper (Refereed)
Abstract [en]

This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.

Place, publisher, year, edition, pages
Tampere: www.ieee.org, 2010
Keywords
CMOS analog integrated circuits, feedforward amplifiers, switched capacitor circuits, programmable gain amplifier.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70366 (URN)10.1109/NORCHIP.2010.5669450 (DOI)978-1-4244-8971-8 (ISBN)978-1-4244-8972-5 (ISBN)
Conference
NORCHIP'10, 15-16 November 2010,Tampere, Finland
Available from: 2011-09-03 Created: 2011-09-03 Last updated: 2018-11-08
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