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Andersson, N. (2015). Design of Integrated Building Blocks for the Digital/Analog Interface. (Doctoral dissertation). Linköping: Linköping University Electronic Press
Open this publication in new window or tab >>Design of Integrated Building Blocks for the Digital/Analog Interface
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The integrated circuit has, since it was invented in the late 1950's, undergone a tremendous development and is today found in virtually all electric equipment. The small feature size and low production cost have made it possible to implement electronics in everyday objects ranging from computers and mobile phones to smart prize tags. Integrated circuits are typically used for data communication, signal processing and data storage. Data is usually stored in digital format but signal processing can be performed both in the digital and in the analog domain. For best performance, the right partition of signal processing between the analog and digital domain must be used. This is made possible by data converters converting data between the domains. A device converting an analog signal into a digital representation is called an analog-to-digital converter (ADC) and a device converting digital data into an analog representation is called a digital-to-analog converter (DAC). In this work we present research results on these data converters and the results are compiled in three different categories. The first contribution is an error correction technique for DACs called dynamic element matching, the second contribution is a power efficient time-to-digital converter architecture and the third is a design methodology for frequency synthesis using digital oscillators.

The accuracy of a data converter, i.e., how accurate data is converted, is often limited by manufacturing errors. One type of error is the so-called matching error and in this work we investigate an error correction technique for DACs called dynamic element matching (DEM). If distortion is limiting the performance of a DAC, the DEM technique increases the accuracy of the DAC by transforming the matching error from being signal dependent, which results in distortion, to become signal independent noise. This noise can then be spectrally shaped or filtered out and hereby increasing the overall resolution of the system. The DEM technique is investigated theoretically and the theory is supported by measurement results from an implemented 14-bit DAC using DEM. From the investigation it is concluded that DEM increases the performance of the DAC when matching errors are dominating but has less effect at conversion speeds when dynamic errors dominate.

The next contribution is a new time-to-digital converter (TDC) architecture. A TDC is effectively an ADC converting a time difference into a digital representation. The proposed architecture allows for smaller and more power efficient data conversion than previously reported and the implemented TDC prototype is smaller and more power efficient as compared to previously published TDCs in the same performance segment.

The third contribution is a design methodology for frequency synthesis using digital oscillators. Digital oscillators generate a sinusoidal output using recursive algorithms. We show that the performance of digital oscillators, in terms of amplitude and frequency stability, to a large extent depends on the start conditions of the oscillators. Further we show that by selecting the proper start condition an oscillator can be forced to repeat the same output sequence over and over again, hence we have a locked oscillator. If the oscillator is locked there is no drift in amplitude or frequency which are common problems for recursive oscillators not using this approach. To find the optimal start conditions a search algorithm has been developed which has been thoroughly tested in simulations. The digital oscillator output is used for test signal generation for a DAC or used to generate tones with high spectral purity using DACs.

Abstract [sv]

Den integrerade kretsen har sedan den uppfanns i slutet av 1950-talet genomgått en enorm utveckling och återfinns idag i princip i all elektronisk utrustning. Den lilla storleken och den låga produktionskostnaden har gjort det möjligt att integrera elektronik i vardagsföremål som datorer och mobiltelefoner och enklare system som till exempel smarta etiketter. Typiska användningsområden för integrerade kretsar är datakommunikation, signalbehandling och datalagring. Data lagras vanligtvis i digitalt format men signalbehandling kan utföras i både den digitala och i den analoga domänen. För att nå bästa prestanda i en krets måste signalbehandlingen delas upp optimalt mellan den digitala och analoga domänen Denna uppdelning möjliggörs med hjälp av dataomvandlare som översätter data mellan de två domänerna. En krets som omvandlar en analog signal till en digital motsvarighet kallas för en analogtill-digital-omvandlare och en krets som ovandlar digitalt data till en analog signal kallas för en digital-till-analog-omvandlare. Denna doktorsavhandling innehåller resultat från forskning gjord på dessa dataomvandlare och resultaten är sammanfattade i tre huvudkategorier. Det första bidraget är en felkorrigeringsmetod för digitaltill-analog-omvandlare, det andra bidraget är en kretsarkitektur för en energieffektiv tid-till-digital-omvandlare och det tredje bidraget är en konstruktionsmetodik för frekvenssyntes med hjälp av digitala svängningskretsar.

Noggrannheten hos en dataomvandlare, med andra ord hur noggrannt dataomvandlaren kan omvandla data mellan de två domänerna, begränsas ofta av de fel som uppstår vid tillverkningen av den integrerade kretsen. En typ av fel som uppstår är att dataomvandlarens jämförelsenivåer inte blir lika stora. I frekvensdomänen kommer denna typ av fel resultera i icke önskade harmoniska frekvenser (distorsion) som begränsar dataomvandlarens noggrannhet. Om distorsion, som uppkommer då ett fel beror på dataomvandlarens insignal, begränsar dataomvandlarens prestanda kan den föreslagna felkorrigeringsmetoden omvandla distortionen till brus genom att göra felet oberoende av insignalen. Det resulterande bruset kan sedan formas spektralt eller filteras bort och därmed öka systemets totala prestanda. Den föreslagna korrigeringsmetiden har undersökts teoretiskt och denna teori har sedan verifierats med mätresultat från en kretsimplementation av en 14-bitars digital-till-analog-omvandlare som använder den föreslagna felkorrigeringsmetoden. Mätresultaten visar att metod en höjer prestandan hos dataomvandlaren för låga insignalfrekvenser då det är felen i jämförelsenivåerna som begränsar prestandan. Vid högre insignalfrekvenser är metoden mindre effektiv då andra dynamiska felkällor hos dataomvandlaren istället begränsar noggranheten.

Nästa bidrag är en kretsarkitektur till en tid-till-digital-omvandlare. En tid-tilldigital-omvandlare är en särskild sorts analog-till-digital-omvandlare som omvandlar tidsskillanden mellan två signaler till en digital representation. Mätresultat från en kretsprototyp visar att den föreslagna kretsarkitekturen är både mindre och mer energieffektiv än tidigare publicerade kretslösningar.

Det tredje bidraget är en konstruktionsmetodik för frekvenssyntes med hjälp av digitala svängningskretsar (oscillatorer). De digitala oscillatorerna genererar en sinusformad utsignal med hjälp av rekursiva algoritmer. Vi visar att prestandan hos digitala oscillatorer, mätt i termer av amplitud- och frekvensstabilitet, till stor utsträckning beror av starttillstånden hos oscillatorerna. Vi visar också att en del starttillstånd tvingar en oscillator att upprepa samma utsignalssekvens om och om igen, vi har då fått vad vi kallar en låst oscillator. Om oscillatorn har låst finns det inte längre någon drift i amplitud eller frekvens vilka är vanliga problem för rekursiva oscillatorer som inte använder denna metod. För att hitta de op timala startvillkoren för oscillatorerna har en sökalgoritm utvecklats. Denna algoritm har testats noggrannt i datorsimuleringar. En digital oscillator är lämplig att användas för testsignalgenerering för digital-tillanalog-omvandlare där kraven på amplitud- och frekvensstabila testsignaler är höga.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2015. p. 100
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1638
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112215 (URN)10.3384/diss.diva-112215 (DOI)978-91-7519-163-8 (ISBN)
Public defence
2015-01-16, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2014-12-04 Created: 2014-11-18 Last updated: 2018-11-08Bibliographically approved
Andersson, N. & Vesterbacka, M. (2015). Power-efficient time-to-digital converter for all-digital frequency locked loops. In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD): . Paper presented at European Conference on Circuit Theory and Design (ECCTD) (pp. 300-303). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Power-efficient time-to-digital converter for all-digital frequency locked loops
2015 (English)In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 300-303Conference paper, Published paper (Refereed)
Abstract [en]

An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This architecture allows for an area efficient and power efficient implementation. Thetarget application for the TDC is an all-digital frequency-locked loop which is alsooverviewed in the paper. A prototype chip has been implemented in a 65 nm CMOSprocess with an active core area of 75μmˆ120μm. The time resolution is 5.7 ps with apower consumption of 1.85 mW measured at 50 MHz sampling frequency.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112589 (URN)10.1109/ECCTD.2015.7300008 (DOI)000380498200010 ()978-1-4799-9877-7 (ISBN)
Conference
European Conference on Circuit Theory and Design (ECCTD)
Available from: 2014-12-04 Created: 2014-12-04 Last updated: 2019-01-07Bibliographically approved
Andersson, N. & Vesterbacka, M. (2014). A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture. IEEE Transactions on Circuits and Systems - II - Express Briefs, 61(10), 773-777
Open this publication in new window or tab >>A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
2014 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 10, p. 773-777Article in journal (Refereed) Published
Abstract [en]

A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2014
Keywords
CMOS; delay latch; time-to-digital converter (TDC); Vernier
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112180 (URN)10.1109/TCSII.2014.2345289 (DOI)000343320500009 ()
Available from: 2014-11-18 Created: 2014-11-18 Last updated: 2017-12-05
Andersson, N., Vesterbacka, M., Gustafsson, O. & Wikner, J. (2014). Steady-state cycles in digital oscillators.
Open this publication in new window or tab >>Steady-state cycles in digital oscillators
2014 (English)Manuscript (preprint) (Other academic)
Abstract [en]

Digital recursive oscillators locked in steady-state can be used to generate sinusoids with high spectral purity. The locking occurs when the oscillator returns to a previously visited state and repeats its sequence. In this work we propose a new search algorithm and two new search strategies to find all steady-states for a given oscillator configuration. The improvement in spurious-free dynamic range is between 7 and 40 dB compared to previously reported results. The algorithm is also able to find oscillator sequences for more frequencies than previously reported work. A key part of the method is the reduction of the search space made possible by a proposed extension of existing theory on recursive oscillators. Specific properties of digital oscillators in a steady-state are also discussed. It is shown that the initial states can be used to individually control the phase, amplitude, spectral purity, and also cycle length of the oscillator output.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112590 (URN)
Available from: 2014-12-04 Created: 2014-12-04 Last updated: 2018-11-08Bibliographically approved
Jalili, A., Sayedi, S. M., Wikner, J., Andersson, N. & Vesterbacka, M. (2010). Calibration of sigma-delta analog-to-digital converters based on histogram test methods. In: NORCHIP, 2010. Paper presented at NorChip 2010, 28th Norchip Conference, 15 - 16 November 2010, Tampere, Finland (pp. 1-4). IEEE
Open this publication in new window or tab >>Calibration of sigma-delta analog-to-digital converters based on histogram test methods
Show others...
2010 (English)In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which highspeed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied. It is shown that the calibration technique can cope with errors that occur in the feedback digital-to-analog converter (DAC) and the input accumulator. Behavioral-level simulation results show an improvement of in effective number of bits (ENOB) from 6.6 to 11.3. Fairly large offset and gain errors have been introduced which illustrates a robust calibration technique.

Place, publisher, year, edition, pages
IEEE, 2010
Keywords
#x03A3; #x0394; analog-to-digital converters;calibration technique;feedback digital-to-analog converter;histogram test methods;low-resolution flash subADCs;sigma-delta analog-to-digital converters;calibration;feedback;sigma-delta modulation;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70627 (URN)10.1109/NORCHIP.2010.5669459 (DOI)978-1-4244-8972-5 (ISBN)
Conference
NorChip 2010, 28th Norchip Conference, 15 - 16 November 2010, Tampere, Finland
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
Rudberg, M., Vesterbacka, M., Andersson, N. & Wikner, J. (2002). Scrambler and a method of scrambling data words, (US pat. 2002027519). .
Open this publication in new window or tab >>Scrambler and a method of scrambling data words, (US pat. 2002027519)
2002 (English)Patent (Other (popular science, discussion, etc.))
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70649 (URN)
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
Andersson, O., Andersson, N. & Wikner, J. (2001). Spectral shaping of DAC nonlinearity errors through modulation of expected errors. In: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on. Paper presented at The 2001 IEEE International Symposium on Circuits and Systems, (ISCAS'01), 6-9 May 2001, Sydney Australia (pp. 417-420). IEEE, 3
Open this publication in new window or tab >>Spectral shaping of DAC nonlinearity errors through modulation of expected errors
2001 (English)In: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, IEEE , 2001, Vol. 3, p. 417-420Conference paper, Published paper (Refereed)
Abstract [en]

Traditionally, delta-sigma modulation has been used for shaping of quantization noise. We present a modified version of delta-sigma modulation which also takes into account unwanted nonlinearities by feeding back not only the quantization error, but also the expected physical error. Behavioral-level simulations of a 5th-order structure showing an improvement of up to 4 effective bits are included

Place, publisher, year, edition, pages
IEEE, 2001
Keywords
behavioral-level simulation;delta-sigma modulation;digital-analog converter;nonlinearity error feedback;quantization noise;spectral shaping;circuit feedback;delta-sigma modulation;digital-analogue conversion;errors;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70630 (URN)10.1109/ISCAS.2001.921336 (DOI)0-7803-6685-9 (ISBN)
Conference
The 2001 IEEE International Symposium on Circuits and Systems, (ISCAS'01), 6-9 May 2001, Sydney Australia
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
Andersson, N. & Wikner, J. (2000). A strategy for implementing dynamic element matching in current-steering DACs. In: Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on. Paper presented at SSMSD 2000, 27 - 29 Feb. 2000, San Diego, CA , USA (pp. 51-56). IEEE
Open this publication in new window or tab >>A strategy for implementing dynamic element matching in current-steering DACs
2000 (English)In: Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on, IEEE , 2000, p. 51-56Conference paper, Published paper (Other academic)
Abstract [en]

Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS current-steering wideband digital-to-analog converter (DAC)

Place, publisher, year, edition, pages
IEEE, 2000
Keywords
0.35 micron;11 MHz;14 bit;3.3 V;88 MHz;CMOS wideband DAC;current-steering DACs;dynamic element matching;partial randomization technique;wideband digital-to-analog converter;CMOS integrated circuits;digital-analogue conversion;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70637 (URN)10.1109/SSMSD.2000.836445 (DOI)0-7803-5975-5 (ISBN)
Conference
SSMSD 2000, 27 - 29 Feb. 2000, San Diego, CA , USA
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
Andersson, N., Vesterbacka, M., Wikner, J. & Rudberg, M. (2000). Improvement of segmented DACs (Swedish pat. 0001917-4). .
Open this publication in new window or tab >>Improvement of segmented DACs (Swedish pat. 0001917-4)
2000 (English)Patent (Other (popular science, discussion, etc.))
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70650 (URN)
Note
PatentAvailable from: 2011-09-14 Created: 2011-09-14 Last updated: 2018-11-08
Andersson, N. & Wikner, J. (1999). A comparison of dynamic element matching in DACs. In: Trond Sæther (Ed.), Proceedings '99 : Oslo, Norway, 8-9 November 1999: . Paper presented at The 17th NORCHIP Conference, November 8-9, Oslo, Norway (pp. 385-390).
Open this publication in new window or tab >>A comparison of dynamic element matching in DACs
1999 (English)In: Proceedings '99 : Oslo, Norway, 8-9 November 1999 / [ed] Trond Sæther, 1999, p. 385-390Conference paper, Published paper (Other academic)
Abstract [en]

In the field of dynamic element matching, DEM, techniques, some "new" important theoretical results have been presented during the last decade. However, no comparison between these different DEM techniques (FRDEM, PRDEM, NSDEM) used in wideband digital-to-analog converters, DACs, has been reported. A brief review of different DEM techniques and a comparison between their properties in terms of complexity, etc., are presented in this paper together with simulation results showing the impact of using different DEM techniques.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112582 (URN)8798263722 (ISBN)
Conference
The 17th NORCHIP Conference, November 8-9, Oslo, Norway
Available from: 2014-12-04 Created: 2014-12-04 Last updated: 2018-11-08Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0001-6123-9881

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