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Chattopadhyay, Sudipta
Publications (9 of 9) Show all publications
Banerjee, A., Chattopadhyay, S. & Roychoudhury, A. (2016). On Testing Embedded Software. Advances in Computers, 101, 121-153
Open this publication in new window or tab >>On Testing Embedded Software
2016 (English)In: Advances in Computers, ISSN 0065-2458, Vol. 101, p. 121-153Article in journal (Refereed) Published
Abstract [en]

For the last few decades, embedded systems have expanded their reach into major aspects of human lives. Starting from small handheld devices (such as smartphones) to advanced automotive systems (such as anti-lock braking systems), usage of embedded systems has increased at a dramatic pace. Embedded software are specialized software that are intended to operate on embedded devices. In this chapter, we shall describe the unique challenges associated with testing embedded software. In particular, embedded software are required to satisfy several non-functional constraints, in addition to functionality-related constraints. Such non-functional constraints may include (but not limited to), timing/energy-consumption related constrains or reliability requirements, etc. Additionally, embedded systems are often required to operate in interaction with the physical environment, obtaining their inputs from environmental factors (such as temperature or air pressure). The need to interact with a dynamic, often non-deterministic physical environment, further increases the challenges associated with testing, and validation of embedded software. In the past, testing and validation methodologies have been studied extensively. This chapter, however, explores the advances in software testing methodologies, specifically in the context of embedded software. This chapter introduces the reader to key challenges in testing non-functional properties of software by means of realistic examples. It also presents an easy-to-follow, classification of existing research work on this topic. Finally, the chapter is concluded with a review of promising future directions in the area of embedded software testing.

Place, publisher, year, edition, pages
Elsevier, 2016
Keywords
Non-functional property testing, Performance testing, Energy consumption of software, Search-based software testing, Symbolic execution
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-124542 (URN)10.1016/bs.adcom.2015.11.005 (DOI)
Available from: 2016-02-02 Created: 2016-02-02 Last updated: 2018-01-10
Jiang, K., Eles, P., Peng, Z., Chattopadhyay, S. & Batina, L. (2016). SPARTA: A scheduling policy for thwarting differential power analysis attacks. In: 2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC): . Paper presented at 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). 25-28 Jan. 2016 Macau (pp. 667-672). IEEE Press
Open this publication in new window or tab >>SPARTA: A scheduling policy for thwarting differential power analysis attacks
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2016 (English)In: 2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), IEEE Press, 2016, p. 667-672Conference paper, Published paper (Refereed)
Abstract [en]

Embedded systems (ESs) have been widely used in various application domains. It is very important to design ESs that guarantee functional correctness of the system under strict timing constraints. Such systems are known as the real-time embedded systems (RTESs). More recently, RTESs started to be utilized in safety and reliability critical areas, which made the overlooked security issues, especially confidentiality of the communication, a serious problem. Differential power analysis attacks (DPAs) pose serious threats to confidentiality protection mechanisms, i.e., implementations of cryptographic algorithms, on embedded platforms. In this work, we present a scheduling policy, SPARTA, that thwarts DPAs. Theoretical guarantees and preliminary experimental results are presented to demonstrate the efficiency of the SPARTA scheduler.

Place, publisher, year, edition, pages
IEEE Press, 2016
Series
Asia and South Pacific Design Automation Conference Proceedings, ISSN 2153-6961
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-129005 (URN)10.1109/ASPDAC.2016.7428088 (DOI)000384642200117 ()978-1-4673-9568-7 (ISBN)
Conference
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). 25-28 Jan. 2016 Macau
Available from: 2016-06-08 Created: 2016-06-08 Last updated: 2018-01-10
Horga, A., Chattopadhyay, S., Eles, P. & Peng, Z. (2016). Systematic detection of memory related performance bottlenecks in GPGPU programs. Journal of systems architecture, 71, 73-87
Open this publication in new window or tab >>Systematic detection of memory related performance bottlenecks in GPGPU programs
2016 (English)In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 71, p. 73-87Article in journal (Refereed) Published
Abstract [en]

Graphics processing units (GPUs) pose an attractive choice for designing high-performance and energy-efficient software systems. This is because GPUs are capable of executing massively parallel applications. However, the performance of GPUs is limited by the contention in memory subsystems, often resulting in substantial delays and effectively reducing the parallelism. In this paper, we propose GRAB, an automated debugger to aid the development of efficient GPU kernels. GRAB systematically detects, classifies and discovers the root causes of memory-performance bottlenecks in GPUs. We have implemented GRAB and evaluated it with several open-source GPU kernels, including two real-life case studies. We show the usage of GRAB through improvement of GPU kernels on a real NVIDIA Tegra K1 hardware – a widely used GPU for mobile and handheld devices. The guidance obtained from GRAB leads to an overall improvement of up to 64%.

Place, publisher, year, edition, pages
Elsevier, 2016
Keywords
Performance debugging, GPGPU, Caches
National Category
Computer Sciences
Identifiers
urn:nbn:se:liu:diva-131079 (URN)10.1016/j.sysarc.2016.08.002 (DOI)000390503600008 ()
Available from: 2016-09-07 Created: 2016-09-07 Last updated: 2018-01-10Bibliographically approved
Chattopadhyay, S. (2015). MESS: Memory Performance Debugging on Embedded Multi-core Systems. In: Bernd Fischer; Jaco Geldenhuys (Ed.), Model Checking Software: 22nd International Symposium, SPIN 2015: . Paper presented at 22nd International SPIN Symposium on Model Checking of Software (SPIN), Stellenbosch, South Africa, August 24-26, 2015 (pp. 105-125). Springer Berlin/Heidelberg, 9232
Open this publication in new window or tab >>MESS: Memory Performance Debugging on Embedded Multi-core Systems
2015 (English)In: Model Checking Software: 22nd International Symposium, SPIN 2015 / [ed] Bernd Fischer; Jaco Geldenhuys, Springer Berlin/Heidelberg, 2015, Vol. 9232, p. 105-125Conference paper, Published paper (Refereed)
Abstract [en]

Multi-core processors have penetrated the modern computing platforms in several dimensions. Such systems aim to achieve high-performance via running computations in parallel. However, the performance of such systems is often limited due to the congestion in shared resources, such as shared caches and shared buses. In this paper, we propose MESS, a performance debugging framework for embedded, multi-core systems. MESS systematically discovers the order of memory-access operations that expose performance bugs due to shared caches. We leverage both on single-core performance profiling and symbolic constraint solving to reveal the interleaved memory-access-pattern that leads to a performance bug. Our baseline framework does not generate any false positive. Besides, its failure to find a solution highlights the absence of performance bugs due to shared caches, for a given input. Finally, we propose an approximate solution that dramatically reduces debugging time, at the cost of a reasonable amount of false positives. Our experiments with several embedded software and a real-life robot controller suggest that we can discover performance bugs in a reasonable time. The implementation of MESS and our experiments are available at https://bitbucket.org/sudiptac/mess.

Place, publisher, year, edition, pages
Springer Berlin/Heidelberg, 2015
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 9232
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-122795 (URN)10.1007/978-3-319-23404-5_8 (DOI)000363788300008 ()978-3-319-23404-5 (ISBN)978-3-319-23403-8 (ISBN)
Conference
22nd International SPIN Symposium on Model Checking of Software (SPIN), Stellenbosch, South Africa, August 24-26, 2015
Available from: 2015-11-23 Created: 2015-11-23 Last updated: 2018-02-23
Chattopadhyay, S., Kee Chong, L., Roychoudhury, A., Kelter, T., Marwedel, P. & Falk, H. (2014). A Unified WCET Analysis Framework for Multicore Platforms. ACM Transactions on Embedded Computing Systems, 13(124)
Open this publication in new window or tab >>A Unified WCET Analysis Framework for Multicore Platforms
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2014 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 13, no 124Article in journal (Refereed) Published
Abstract [en]

With the advent of multicore architectures, worst-case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic microarchitectural components (e.g., pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multicore architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2014
Keywords
Design; Performance; Verification; WCET; shared cache; shared bus; multicore
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-111298 (URN)10.1145/2584654 (DOI)000341390100007 ()
Note

Funding Agencies|A*STAR public sector funding project from Singapore [1121202007, R252-000-476-305]; ArtistDesign Network of Excellence (the European Community) [216008]; Deutsche Forschungsgemeinschaft (DFG) [FA 1017/1-1]

Available from: 2014-10-14 Created: 2014-10-14 Last updated: 2018-01-11Bibliographically approved
Chattopadhyay, S., Eles, P. & Peng, Z. (2014). Automated software testing of memory performance in embedded GPUs. In: EMSOFT 2014: . Paper presented at 14th International Conference on Embedded Software (EMSOFT 2014), New Delhi, India, October 12-17, 2014. Association for Computing Machinery (ACM)
Open this publication in new window or tab >>Automated software testing of memory performance in embedded GPUs
2014 (English)In: EMSOFT 2014, Association for Computing Machinery (ACM), 2014Conference paper, Published paper (Refereed)
Abstract [en]

Embedded and real-time software is often constrained by several temporal requirements. Therefore, it is important to design embedded software that meets the required performance goal. The inception of embedded graphics processing units (GPUs) brings new light in developing high-performance embedded software which were previously not suitable for embedded platforms. Whereas GPUs use massive parallelism to obtain high throughput, the overall performance of an application running on embedded GPUs is often limited by memory performance. Therefore, a crucial problem lies in automatically detecting the inefficiency of such software developed for embedded GPUs. In this paper, we propose GUPT, a novel test generation framework that systematically explores and detects poor memory performance of applications running on embedded GPUs. In particular, we systematically combine static analysis with dynamic test generation to expose likely execution scenarios with poor memory performance. Each test case in our generated test suite reports a potential memory-performance issue, along with the detailed information to reproduce the same. We have implemented our test generation framework using GPGPU-Sim, a cycle-accurate simulator and the LLVM compiler infrastructure.We have evaluated our framework for several open-source programs. Our experiments suggest the efficacy of our framework by exposing numerous memory-performance issues in a reasonable time. We also show the usage of our framework in improving the performance of programs for embedded GPUs.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2014
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-112684 (URN)10.1145/2656045.2656047 (DOI)2-s2.0-84910130322 (Scopus ID)978-1-4503-3052-7 (ISBN)
Conference
14th International Conference on Embedded Software (EMSOFT 2014), New Delhi, India, October 12-17, 2014
Available from: 2014-12-08 Created: 2014-12-08 Last updated: 2018-01-11Bibliographically approved
Chattopadhyay, S. & Roychoudhury, A. (2014). Cache-Related Preemption Delay Analysis for Multilevel Noninclusive Caches. ACM Transactions on Embedded Computing Systems, 13(147)
Open this publication in new window or tab >>Cache-Related Preemption Delay Analysis for Multilevel Noninclusive Caches
2014 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 13, no 147Article in journal (Refereed) Published
Abstract [en]

With the rapid growth of complex hardware features, timing analysis has become an increasingly difficult problem. The key to solving this problem lies in the precise and scalable modeling of performance-enhancing processor features (e.g., cache). Moreover, real-time systems are often multitasking and use preemptive scheduling, with fixed or dynamic priority assignment. For such systems, cache related preemption delay (CRPD) may increase the execution time of a task. Therefore, CRPD may affect the overall schedulability analysis. Existing works propose to bound the value of CRPD in a single-level cache. In this article, we propose a CRPD analysis framework that can be used for a two-level, noninclusive cache hierarchy. In addition, our proposed framework is also applicable in the presence of shared caches. We first show that CRPD analysis faces several new challenges in the presence of a multilevel, noninclusive cache hierarchy. Our proposed framework overcomes all such challenges and we can formally prove the correctness of our framework. We have performed experiments with several subject programs, including an unmanned aerial vehicle (UAV) controller and an in-situ space debris monitoring instrument. Our experimental results suggest that we can provide sound and precise CRPD estimates using our framework.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2014
Keywords
Design; Performance; Verification; Cache-related preemption delay; WCET; multilevel caches; multicore; shared caches
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-113373 (URN)10.1145/2632156 (DOI)000346416300003 ()
Note

Funding Agencies|A*STAR Public Sector Funding "Scalable Timing Analysis Methods for Embedded Software" [1121202007]

Available from: 2015-01-16 Created: 2015-01-16 Last updated: 2018-01-11
Banerjee, A., Chong, L. K., Chattopadhyay, S. & Roychoudhury, A. (2014). Detecting Energy Bugs and Hotspots in Mobile Apps. In: FSE 2014: Foundations of Software Engineering. Paper presented at 22nd ACM SIGSOFT International Symposium on Foundations of Software Engineering (FSE 2014), Hong Kong, China, November 16-21, 2014 (pp. 588-598). Association for Computing Machinery (ACM)
Open this publication in new window or tab >>Detecting Energy Bugs and Hotspots in Mobile Apps
2014 (English)In: FSE 2014: Foundations of Software Engineering, Association for Computing Machinery (ACM), 2014, p. 588-598Conference paper, Published paper (Refereed)
Abstract [en]

Over the recent years, the popularity of smartphones has increased dramatically. This has lead to a widespread availability of smartphone applications. Since smartphones operate on a limited amount of battery power, it is important to develop tools and techniques that aid in energy-efficient application development. Energy inefficiencies in smartphone applications can broadly be categorized into energy hotspots and energy bugs. An energy hotspot can be described as a scenario where executing an application causes the smartphone to consume abnormally high amount of battery power, even though the utilization of its hardware resources is low. In contrast, an energy bug can be described as a scenario where a malfunctioning application prevents the smartphone from becoming idle, even after it has completed execution and there is no user activity. In this paper, we present an automated test generation framework that detects energy hotspots/bugs in Android applications. Our framework systematically generates test inputs that are likely to capture energy hotspots/bugs. Each test input captures a sequence of user interactions (e.g. touches or taps on the smartphone screen) that leads to an energy hotspot/bug in the application. Evaluation with 30 freely-available Android applications from Google Play/F-Droid shows the efficacy of our framework in finding hotspots/bugs. Manual validation of the experimental results shows that our framework reports reasonably low number of false positives. Finally, we show the usage of the generated results by improving the energy-efficiency of some Android applications.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2014
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-112688 (URN)10.1145/2635868.2635871 (DOI)978-1-4503-3056-5 (ISBN)
Conference
22nd ACM SIGSOFT International Symposium on Foundations of Software Engineering (FSE 2014), Hong Kong, China, November 16-21, 2014
Available from: 2014-12-08 Created: 2014-12-08 Last updated: 2018-01-11Bibliographically approved
Chattopadhyay, S., Roychoudhury, A., Rosén, J., Eles, P. & Peng, Z. (2014). Time-Predictable Embedded Software on Multi-Core Platforms: Analysis and Optimization. Foundations and Trends in Electronic Design Automation, 8(3-4), 199-356
Open this publication in new window or tab >>Time-Predictable Embedded Software on Multi-Core Platforms: Analysis and Optimization
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2014 (English)In: Foundations and Trends in Electronic Design Automation, ISSN 1551-3939, Vol. 8, no 3-4, p. 199-356Article in journal (Refereed) Published
Abstract [en]

Multi-core architectures have recently gained popularity due to their high-performance and low-power characteristics. Most of the modern desktop systems are now equipped with multi-core processors. Despite the wide-spread adaptation of multi-core processors in desktop systems, using such processors in embedded systems still poses several challenges. Embedded systems are often constrained by several extra-functional aspects, such as time. Therefore, providing guarantees for time-predictable execution is one of the key requirements for embedded system designers. Multi-core processors adversely affect the time-predictability due to the presence of shared resources, such as shared caches and shared buses. In this contribution, we shall first discuss the challenges imposed by multi-core architectures in designing time-predictable embedded systems. Subsequently, we shall describe, in details, a comprehensive solution to guarantee time-predictable execution on multi-core platforms. Besides, we shall also perform a discussion of different techniques to provide an overview of the state-of-the-art solutions in this topic. Through this work, we aim to provide a solid background on recent trends of research towards achieving time-predictability on multi-cores. Besides, we also highlight the limitations of the state-of-the-art and discuss future research opportunities and challenges to accomplish time-predictable execution on multi-core platforms.

National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:liu:diva-112687 (URN)10.1561/1000000037 (DOI)
Available from: 2014-12-08 Created: 2014-12-08 Last updated: 2018-01-11Bibliographically approved
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