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Unnikrishnan, Vishnu
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Unnikrishnan, V. & Vesterbacka, M. (2014). Time-Mode Analog-to-Digital Conversion Using Standard Cells. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 61(12), 3348-3357
Open this publication in new window or tab >>Time-Mode Analog-to-Digital Conversion Using Standard Cells
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 12, p. 3348-3357Article in journal (Refereed) Published
Abstract [en]

Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2014
Keywords
ADC; all-digital; analog-to-digital; Gray-counter; linearization; polynomial-fit; standard cell; synthesizable; time-domain; time-mode; VCO-based ADC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113048 (URN)10.1109/TCSI.2014.2340551 (DOI)000345581200004 ()
Available from: 2015-01-09 Created: 2015-01-08 Last updated: 2017-12-05
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