Electronic devices with wireless connectivity are fast becoming a part of daily life. According to some estimates, in the next five years, 10 billion new devices with internet connectivity would be produced. To lower the costs and extend the battery life of electronic circuits, there is an increased interest in using lowcost, low-power CMOS circuits. By taking advantage of the higher integration capabilities of modern CMOS, the analog, digital, and radio circuits can be integrated on a single die, typically called a radio-frequency system-on-chip (RF-SoC).

In an RF-SoC, most of the power is usually consumed by the radio circuits, especially the power amplifier (PA). Hence, to take advantage of the improved switching capability of transistors in modern CMOS, the use of switch-mode PAs (SMPAs) is becoming more popular. SMPAs exhibit a much higher efficiency as compared to their linear counterparts and can be easily integrated with the digital baseband circuits.

To satisfy the demand for higher data throughput, modern wireless standards like LTE and IEEE 802.11 generate envelope-varying signals using advanced modulation schemes like M-QAM and OFDM. Among several other techniques, pulse-width modulation (PWM) allows for the amplification of the envelopevarying signals using SMPAs.

The first part of this thesis explores techniques to improve the spectral performance of PWM-based transmitters. The proposed transmitters are fully digital, and the entire signal chain up to the PA can be implemented using the digital design flow, which is especially beneficial in sub-micron CMOS processes with low voltage headroom. A new transmitter is proposed that compensates for the aliasing distortion in polar PWM transmitters by using outphasing. The transmitter exhibits an improvement of up to 9 dB in dynamic range for a 1.4 MHz LTE uplink signal. The idea is extended to compensate for both image and aliasing distortions in all-digital implementations of polar PWM transmitters. By using a field programmable gate array (FPGA) and Class-D SMPAs, the proposed transmitter shows an improvement of up to 6.9 dBc in the adjacent channel leakage ratio (ACLR) and 10% in the error vector magnitude (EVM) for a 20 MHz LTE uplink signal. The proposed transmitter is fully programmable and can be easily adapted for multi-band and multi-standard transmission.

To enhance the phase linearity of all-digital PWM transmitters, a new transmitter architecture based on outphasing is presented. The proposed transmitter uses outphasing to improve the phase resolution and exhibits an improvement of 2.8 dBc and 3.3% in ACLR and EVM, respectively.

The difference between the polar and quadrature implementations of RFPWM based transmitters is explored. By using mathematical derivations and simulations, it is shown that the polar implementation outperforms the quadrature implementation due to the lower quantization noise. An RF-PWM based transmitter that eliminates both image and aliasing distortions is presented. The proposed transmitter has an all-digital implementation, uses a single SMPA, and eliminates the need for a power combiner resulting in a more compact design. For a 1.4 MHz LTE uplink signal, the proposed transmitter exhibits an improvement of up to 11.3 dBc in ACLR.

The second part of this work focuses on the design of all-digital area-efficient architectures of time-to-digital converters (TDCs). A TDC is essentially a stopwatch with a pico-second resolution and can be used to accurately quantify the pulse width and position of PWM signals.

A Vernier delay line-based TDC is presented that replaces the conventionally used sampling D flip-flops by a single transistor. This resulting implementation does not suffer from blackout time associated with D flip-flops allowing for a more compact design. The proposed TDC achieves a time resolution of 5.7 ps, and consumes 1.85 mW of power while operating at 50 MS/s.

A modified switching scheme to reduce the power consumed by the thermometerto- binary encoder used in the TDCs is presented. By taking advantage of the operating nature of the TDCs, the proposed switching scheme reduces the power consumption by up to 40% for a 256-bit encoder.

Trådlös elektronik har snabbt blivit en del av vår vardag. Enligt uppskattningar kommer tio miljarder nya enheter anslutas till internet de närmaste fem åren. För billig och strömsnål elektronik vill man gärna använda CMOS-kretsar. Genom att utnyttja den höga integrationsförmågan med CMOS kan digitala, analoga och radiokretsar läggas samman på ett enda chip, kallat ett RF-SoC (Radio Frequency System-on-Chip).

Den största energiförbrukningen i ett RF-SoC är oftast i radiokretsarna, speciellt i sändarförstärkaren. Genom att utnyttja de allt snabbare CMOStransistorerna kan switchade förstärkare användas. Dessa har mycket mindre energiförluster jämfört med sina linjära motsvarigheter och kan enkelt integreras med digitala elektronik i en CMOS-krets.

För att tillgodose efterfrågan på högre dataöverföring används i modern trådlös datakommunikation signaler med varierande amplitud och fas samt hög bandbredd. Om vi skall kunna använda switchade förstärkare med sådana signaler, måste sändarnas arkitektur anpassas. Pulsbreddsmodulering (PWM) är en teknik som möjliggör detta.

Den första delen av denna avhandling undersöker tekniker för att förbättra spektralprestandan hos PWM-baserade sändare. De föreslagna sändarna kan konstrueras med helt digitala kretsblock fram till sändarförstärkaren.

En ny sändararkitektur som kompenserar för spegelförvrängning i polära PWM-sändare genom att använda utfasning (en klassisk teknik i äldre förstärkare) har studerats. Arkitekturen har förbättras för att kompensera för olika typer av förvrängningar av signalen som ofta uppkommer i konventionella digitala polära PWM-sändare. Genom att använda en Field-Programmable Gate Array (FPGA, ’på-plats-programmerbar grindmatris’) och switchade klass Dförstärkare, har viktiga sändarparametrar i den föreslagna sändaren förbättrats. Sändaren är helt programmerbar och kan enkelt anpassas för multiband- och multistandard-sändning.

För att förbättra faslinjäriteten hos digitala PWM-sändare presenteras en ny sändararkitektur baserad på utfasning i avhandlingen.

Skillnaden mellan polära och kvadraturimplementeringar av RF-PWMbaserade sändare har undersökts. Genom matematiska härledningar och simuleringar visar det sig att den polära implementeringen är bättre än kvadraturimplementering på grund av det lägre kvantiseringsbruset. En RF-PWM-baserad sändare som eliminerar både spegelförvrängningar och vikningsdistorsion presenteras. Den föreslagna sändaren är helt digital, använder en enda switchad förstärkare och kan konstrueras utan den annars nödvändiga effektkombineraren, vilket resulterar i en mer kompakt konstruktion.

Den andra delen av detta avhandlingsarbetet är inriktat på utformningen av helt digitala yteffektiva arkitekturer av tid-till-digital-omvandlare (time-to-digital converter, TDC). En TDC är i huvudsak ett stoppur med picosekundsupplösning och kan användas för att exakt kvantifiera pulsbredd och position för PWMsignaler.

En Vernier-fördröjningsbaserad TDC presenteras som ersätter de samplade D-vippor som brukar användas i sådana kretsar med en enda transistor. Den föreslagna kretsen lider inte av dödtider som kretsar baserade på D-vippor gör, vilket möjliggör en mer kompakt design.

Ett modifierat växlingsschema för att reducera effektförbrukningen i termometertill- binär-kodare som används i TDC:er föreslås. Genom att utnyttja TDC:ns karakteristiska beteende kan strömförbrukningen minskas med upp till 40% för en 256-bitars kodare.  

Linearity and efficiency are important parameters in determining the performance of any wireless transmitter. Pulse-width modulation (PWM) based transmitters offer high efficiency but suffer from low linearity due to image and aliasing distortions. Although the problem of linearity can be addressed by using an aliasing-free PWM (AF-PWM), these transmitters have a lower efficiency as they can only use linear power amplifiers (PAs). Moreover, an all-digital implementation of such transmitters is not possible. The aliasing-compensated PWM transmitter (AC-PWMT) has a higher efficiency due to the use of switch-mode PAs (SMPAs) but uses outphasing to eliminate image and aliasing distortions and requires a larger silicon area. In this study, the authors propose a novel transmitter that eliminates both aliasing and image distortions while using a single SMPA. The transmitter can be implemented using all-digital techniques and achieves a higher efficiency as compared to both AF-PWM and AC-PWM based transmitters. Measurement results show an improvement of 11.3, 7.2, and 4.3 dBc in the ACLR as compared to the carrier-based PWM transmitter (C-PWMT), AF-PWMT, and AC-PWMT, respectively. The efficiency of the proposed transmitter is similar to that of C-PWMT, which is an improvement of 5% over AF-PWMT.

All-digital implementations of PWM-based wireless transmitters are gaining popularity. Unlike baseband PWM, RF-PWM has relaxed filtering requirements and is preferred due to a smaller chip size. This paper is aimed to highlight the differences between polar and quadrature implementations of RF-PWM-based transmitters. Using mathematical models and simulations, performance of the two implementations is compared. The mathematical analysis indicates that the quadrature implementation is expected to have higher quantization noise compared to the polar because of the shorter duty cycles at maximum amplitude. The simulations, using a 10 MHz LTE uplink signal at 2 GHz carrier frequency, confirm this and also show the effect of RF pulse swallowing on the error vector magnitude (EVM).

A technique to abbreviate the supply sensitivity of CMOS ring oscillators is presented. By switching the power source from the noisy power supply to a battery during sensitive zero crossings the noise performance of the ring oscillator is improved. The proposed technique can be used in conjunction with other regulation techniques to enhance the performance of ring oscillators in phase locked loops. The proposed switching circuit using a pseudo differential ring oscillator are designed in a 65 nm CMOS process to demonstrate the viability of the proposed scheme in deep submicron process with reduced voltage headroom. At 2 GHz the outputclock exhibits a jitter of less than 14 ps while subjected to a 500 mV noise tone at 500 MHz.

The market for low cost portable electronics is rapidly growing. Physical activity monitors, portable music players, and smart watches are fast becoming a part of daily life. As the market for wearable devices has grown, a primary concern for IC manufacturers is to provide low cost, low power and lightweight circuit solutions. In a bid to lower the costs and extend battery life there is an increased interest in using low-cost, low-power CMOS processes. As a result fully integrated systems on chips (SOC) have been realized that efficiently perform the required functions. These SOCs house digital, analog and in some cases radio circuits on a single die in a bid to reduce cost and improve productivity.

Phase Locked Loops (PLLs) are a key building block for all SOCs where they are used to generate clock signals for synchronous systems. In monolithic implementations the design cost of a circuit is measured in terms of the silicon area and not the number of devices in the circuit. With the advent of all-digital techniques, there is a renewed interest in the design of compact PLLs as the area occupied by the traditional PLLs is very large due to the presence of large passive components in the loop filter and the oscillator. As a result, various digital circuit design techniques are being explored to design compact all-digital PLLs (ADPLLs) while satisfying the performance requirements for the target applications.

The focus of this work is to explore new techniques for area, power and time efficient design of ADPLL component blocks. The first part of this works focuses on the feasibility of using automatic place and route (P&R) tools to synthesize a time-to-digital converter (TDC). An area efficient TDC is synthesized in a 65 nm CMOS process using automated P&R which exhibits a time resolution of 6.5 ps with an input sampling rate of 100 MS/s while occupying an area of 0.002 mm2. A modified switching scheme is also presented which reduces the power consumption of the thermometer-to-binary encoder by up to 40%.

The second part of this thesis proposes a power supply filter for mitigating the affect of cyclostationary noise on the voltage controlled ring oscillator. The key idea is to raise the impedance in the current supply during the sensitive periods and lower it during insensitive periods of the oscillator operation. To demonstrate the feasibility of the proposed filter, a pseudo differential ring oscillator is designed in a 65 nm CMOS process which exhibits an rms jitter of less than 14 ps at 2.4 GHz in the presence of a 500 mV noise tone in the power supply.

We investigate the synthesis of Vernier delay-line time-to-digital converters (TDCs). A modular approach using a TDC architecture based on multiplexers is proposed. The required circuit components are ordinarystandard cells readily available in most CMOS technologies, which renders the TDC suitable for inter-process portability. To demonstrate the viability of the proposed approach a TDC is synthesized to match the specifications of a custom designed reference TDC, reducing the time for layout from 6 weeks to 2 hours. Both TDCs are designed in a 65 nm CMOS technology and achieve a time resolution in the order of 6 ps and a power consumption of 1.3 mW at a sample rate of 100 MS/s.